Removed g_link_status_check from tech_eth_10g entity.

libraries/technology/eth_10g/tb_tb_tech_eth_10g.vhd

@@ -56,12 +56,11 @@ BEGIN
 -- g_ref_clk_156_period      : TIME := 6.4 ns;                   -- for XAUI
 -- g_data_type               : NATURAL := c_tb_tech_mac_10g_data_type_symbols;
 -- g_verify_link_recovery    : BOOLEAN := TRUE;
--- g_link_status_check       : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "11";
 -- g_use_serial_rx_in        : BOOLEAN := FALSE   -- default FALSE when this tb is ran standalone, else use TRUE to simulate a link between two instances of this tb
 
-  u_no_dut       : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, FALSE,  TRUE, 0, c_644, c_156, c_data_type, TRUE, "11", FALSE) PORT MAP (tb_end_vec(0));
-  u_tech_eth_10g : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, FALSE, FALSE, 0, c_644, c_156, c_data_type, TRUE, "11", FALSE) PORT MAP (tb_end_vec(1));
-  u_sim_eth_10g  : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, FALSE, FALSE, 1, c_644, c_156, c_data_type, TRUE, "11", FALSE) PORT MAP (tb_end_vec(2));
+  u_no_dut       : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, FALSE,  TRUE, 0, c_644, c_156, c_data_type, TRUE, FALSE) PORT MAP (tb_end_vec(0));
+  u_tech_eth_10g : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, FALSE, FALSE, 0, c_644, c_156, c_data_type, TRUE, FALSE) PORT MAP (tb_end_vec(1));
+  u_sim_eth_10g  : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, FALSE, FALSE, 1, c_644, c_156, c_data_type, TRUE, FALSE) PORT MAP (tb_end_vec(2));
   
   p_tb_end : PROCESS
   BEGIN

libraries/technology/eth_10g/tb_tech_eth_10g.vhd

@@ -54,7 +54,6 @@ ENTITY tb_tech_eth_10g IS
     g_ref_clk_156_period      : TIME := 6.4 ns;                   -- for XAUI
     g_data_type               : NATURAL := c_tb_tech_mac_10g_data_type_symbols;
     g_verify_link_recovery    : BOOLEAN := TRUE;
-    g_link_status_check       : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "11";
     g_use_serial_rx_in        : BOOLEAN := FALSE   -- default FALSE when this tb is ran standalone, else use TRUE to simulate a link between two instances of this tb
   );
   PORT (
@@ -287,7 +286,6 @@ BEGIN
       g_sim                 => c_sim,
       g_sim_level           => g_sim_level,
       g_nof_channels        => c_nof_channels,
-      g_link_status_check   => g_link_status_check,
       g_pre_header_padding  => TRUE
     )
     PORT MAP (

libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd

@@ -65,7 +65,6 @@ BEGIN
     g_ref_clk_644_period      => tech_pll_clk_644_period,
     g_ref_clk_156_period      => 6.4 ns,
     g_verify_link_recovery    => FALSE,
-    g_link_status_check       => "11",
     g_use_serial_rx_in        => TRUE
   )
   PORT MAP (
@@ -84,7 +83,6 @@ BEGIN
     g_ref_clk_644_period      => tech_pll_clk_644_period + tech_pll_clk_644_10ppm * g_nof_10ppm,
     g_ref_clk_156_period      => 6.4 ns + 64 fs * g_nof_10ppm,
     g_verify_link_recovery    => FALSE,
-    g_link_status_check       => "11",
     g_use_serial_rx_in        => TRUE
   )
   PORT MAP (