in VHDL

commented out the library for ip_arria10_e1sg component instantiation, this results in the component not being instantiated in simulation since this will cause modelsim to crash. It should not have influence on the synthesis.

use the correct library names in the .../technology/ip_arria10_e1sg
folder

Updated all IP related files to match Quartus 15.0 which uses libraries with _150 in their names instead of -141.

Added g_sim_flash_model to ensure only one instance of flash model, to avoid double driver failure in sim.

Moved the ip_stratixiv single file IP from library ip_stratixiv to separate sub libraries, similar as for ip_arria10. Corrected using the decicated library ip_stratixiv<ip_name>_lib instead of all from ip_stratixiv_lib.

Ported IP for remu (ip_stratixiv_remote_update) and epcs (ip_stratixiv_asmi_parallel) from src/ip in UniBoard to technology/altera/stratixiv and technology/flash in RadioHDL.

Renamed memory_* into tech_memory_*, to more clearly show that the components are IP technology wrappers.

Need to declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.

Ported common RAM, ROM components from /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk to /home/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk.

Ported common RAM, ROM components from /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk to /home/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk.