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Commit 0261b80f authored by Jonathan Hargreaves's avatar Jonathan Hargreaves
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Reodered ports in the package file. Added Arria 10 to the wrappers

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......@@ -62,4 +62,12 @@ BEGIN
PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write);
END GENERATE;
-- Note 1: addr must be 32 bits
-- Note 2: need ports for reset, en4b_addr
-- Note 3: ug_altasmi_parallel.pdf not clear what sce(2 downto 0) is for
gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
u0 : ip_arria10_asmi_parallel
PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write, reset, sce, en4b_addr);
END GENERATE;
END ARCHITECTURE;
......@@ -70,23 +70,23 @@ PACKAGE tech_flash_component_pkg IS
component ip_arria10_asmi_parallel is
port (
clkin : in std_logic := 'X'; -- clk
read : in std_logic := 'X'; -- read
rden : in std_logic := 'X'; -- rden
addr : in std_logic_vector(31 downto 0) := (others => 'X'); -- addr
reset : in std_logic := 'X'; -- reset
sce : in std_logic_vector(2 downto 0) := (others => 'X'); -- sce
dataout : out std_logic_vector(7 downto 0); -- dataout
busy : out std_logic; -- busy
data_valid : out std_logic; -- data_valid
wren : in std_logic := 'X'; -- wren
en4b_addr : in std_logic := 'X'; -- en4b_addr
write : in std_logic := 'X'; -- write
datain : in std_logic_vector(7 downto 0) := (others => 'X'); -- datain
illegal_write : out std_logic; -- illegal_write
sector_erase : in std_logic := 'X'; -- sector_erase
illegal_erase : out std_logic; -- illegal_erase
shift_bytes : in std_logic := 'X' -- shift_bytes
addr : in std_logic_vector(31 downto 0);
clkin : in std_logic;
datain : in std_logic_vector(7 downto 0);
rden : in std_logic;
read : in std_logic;
sector_erase : in std_logic;
shift_bytes : in std_logic;
wren : in std_logic;
write : in std_logic;
busy : out std_logic;
data_valid : out std_logic;
dataout : out std_logic_vector(7 downto 0);
illegal_erase : out std_logic;
illegal_write : out std_logic;
reset : in std_logic;
sce : in std_logic_vector(2 downto 0);
en4b_addr : in std_logic
);
end component ip_arria10_asmi_parallel;
......@@ -95,16 +95,16 @@ PACKAGE tech_flash_component_pkg IS
component ip_arria10_remote_update is
port (
read_param : in std_logic := 'X'; -- read_param
param : in std_logic_vector(2 downto 0) := (others => 'X'); -- param
reconfig : in std_logic := 'X'; -- reconfig
reset_timer : in std_logic := 'X'; -- reset_timer
clock : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
busy : out std_logic; -- busy
data_out : out std_logic_vector(31 downto 0); -- data_out
write_param : in std_logic := 'X'; -- write_param
data_in : in std_logic_vector(31 downto 0) := (others => 'X') -- data_in
clock : in std_logic;
data_in : in std_logic_vector(31 downto 0);
param : in std_logic_vector(2 downto 0);
read_param : in std_logic;
reconfig : in std_logic;
reset : in std_logic;
reset_timer : in std_logic;
write_param : in std_logic;
busy : out std_logic;
data_out : out std_logic_vector(31 downto 0)
);
end component ip_arria10_remote_update;
......
......@@ -58,4 +58,11 @@ BEGIN
PORT MAP (clock, data_in, param, read_param, reconfig, reset, reset_timer, write_param, busy, data_out);
END GENERATE;
-- note 1: data_in and data_out must increase to 32 bits
-- note 2: EPCQ-L1024 not yet supported in IP editor
gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
u0 : ip_arria10_remote_update
PORT MAP (clock, data_in, param, read_param, reconfig, reset, reset_timer, write_param, busy, data_out);
END GENERATE;
END ARCHITECTURE;
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