Moved the ip_stratixiv single file IP from library ip_stratixiv to separate...

Moved the ip_stratixiv single file IP from library ip_stratixiv to separate sub libraries, similar as for ip_arria10. Corrected using the decicated library ip_stratixiv<ip_name>_lib instead of all from ip_stratixiv_lib.

libraries/technology/fifo/tech_fifo_dc.vhd

@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_fifo_lib;
 LIBRARY ip_arria10_fifo_lib;
 
 ENTITY tech_fifo_dc IS

libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd

@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_fifo_lib;
 LIBRARY ip_arria10_fifo_lib;
 
 ENTITY tech_fifo_dc_mixed_widths IS

libraries/technology/fifo/tech_fifo_sc.vhd

@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_fifo_lib;
 LIBRARY ip_arria10_fifo_lib;
 
 ENTITY tech_fifo_sc IS

libraries/technology/flash/tech_flash_asmi_parallel.vhd

@@ -28,7 +28,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_flash_lib;
 
 ENTITY tech_flash_asmi_parallel IS
   GENERIC (

libraries/technology/flash/tech_flash_remote_update.vhd

@@ -28,7 +28,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_flash_lib;
 
 ENTITY tech_flash_remote_update IS
   GENERIC (

libraries/technology/iobuf/tech_iobuf_ddio_in.vhd

@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_ddio_lib;
 LIBRARY ip_arria10_ddio_lib;
 
 ENTITY tech_iobuf_ddio_in IS

libraries/technology/iobuf/tech_iobuf_ddio_out.vhd

@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_ddio_lib;
 LIBRARY ip_arria10_ddio_lib;
 
 ENTITY tech_iobuf_ddio_out IS

libraries/technology/memory/tech_memory_ram_cr_cw.vhd

@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_ram_lib;
 LIBRARY ip_arria10_ram_lib;
 
 ENTITY tech_memory_ram_cr_cw IS

libraries/technology/memory/tech_memory_ram_crw_crw.vhd

@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_ram_lib;
 LIBRARY ip_arria10_ram_lib;
 
 ENTITY tech_memory_ram_crw_crw IS

libraries/technology/memory/tech_memory_ram_crwk_crw.vhd

@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_ram_lib;
 LIBRARY ip_arria10_ram_lib;
 
 ENTITY tech_memory_ram_crwk_crw IS  -- support different port data widths and corresponding address ranges

libraries/technology/memory/tech_memory_ram_r_w.vhd

@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_ram_lib;
 LIBRARY ip_arria10_ram_lib;
 
 ENTITY tech_memory_ram_r_w IS

libraries/technology/memory/tech_memory_rom_r.vhd

@@ -26,7 +26,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_ram_lib;
 LIBRARY ip_arria10_ram_lib;
 
 ENTITY tech_memory_rom_r IS

libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd

@@ -21,7 +21,7 @@
 --------------------------------------------------------------------------------
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_stratixiv_lib;
+LIBRARY ip_stratixiv_transceiver_lib;
 
 LIBRARY IEEE, common_lib, dp_lib;
 USE IEEE.STD_LOGIC_1164.ALL;