tech_flash_asmi_parallel.vhd

-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------

-- Purpose : Active Serial Memory Interface to flash device

LIBRARY ieee, technology_lib;
USE ieee.std_logic_1164.all;
USE work.tech_flash_component_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;

-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_flash_lib;
LIBRARY ip_arria10_asmi_parallel_altera_asmi_parallel_150;
LIBRARY ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151;
--LIBRARY ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_180;

ENTITY tech_flash_asmi_parallel IS
  GENERIC (
    g_technology      : NATURAL := c_tech_select_default;
    g_sim_flash_model : BOOLEAN := FALSE
  );
  PORT (
    addr          : IN STD_LOGIC_VECTOR (tech_flash_addr_w(g_technology)-1 DOWNTO 0);
    clkin         : IN STD_LOGIC ;
    datain        : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    rden          : IN STD_LOGIC ;
    read          : IN STD_LOGIC ;
    sector_erase  : IN STD_LOGIC ;
    shift_bytes   : IN STD_LOGIC ;
    wren          : IN STD_LOGIC ;
    write         : IN STD_LOGIC ;
    busy          : OUT STD_LOGIC ;
    data_valid    : OUT STD_LOGIC ;
    dataout       : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
    illegal_erase : OUT STD_LOGIC ;
    illegal_write : OUT STD_LOGIC ;
    reset         : in  std_logic := '0';
    sce           : in  std_logic_vector(2 downto 0) := (others => '0');
    en4b_addr     : in  std_logic := '0'

  );
END tech_flash_asmi_parallel;


ARCHITECTURE str OF tech_flash_asmi_parallel IS

BEGIN

  gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
    u0 : ip_stratixiv_asmi_parallel
    GENERIC MAP (g_sim_flash_model)
    PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write);
  END GENERATE;
   
  -- Note 1: addr must be 32 bits
  -- Note 2: need ports for reset, en4b_addr
  -- Note 3: ug_altasmi_parallel.pdf not clear what sce(2 downto 0) is for 
  gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
    u0 : ip_arria10_asmi_parallel
    PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write, reset, sce, en4b_addr);
  END GENERATE;

  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
    u0 : ip_arria10_e3sge3_asmi_parallel
    PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write, reset, sce, en4b_addr);
  END GENERATE;
   
  gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
    u0 : ip_arria10_e1sg_asmi_parallel
    PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write, reset, sce, en4b_addr);
  END GENERATE;

END ARCHITECTURE;