Corrected asserting ctlr_mosi.burstbegin for only one clock cycle as specified in the uniphy emi_ip.pdf manual.

Only need to reset the state reg, do not reset the other signals to easy timing closure. Use natural for burst_wr_cnt instead of slv.

Define t_mem_ctlr_mosi/miso in common_mem_pkg, to use that instead of the records defined in tech_ddr_pkg. Also remove t_tech_ddr_addr record because it is not needed.

Use ctlr slv address instead of record address. Separate p_burst_size into wr and rd process and define burstsize as positive. Assign ctlr_mosi.burstsize directly using wr/rd_burst_size, no need for ctlr_mosi_burstsize.

Ported $UNB ddr3.vhd to $RADIOHDL io_ddr.vhd. Initial version, still needs to be compiled and simulated with tb_io_ddr.vhd.