Apply dp_ready FIFO flow control in generate loop, instead of using func_dp_stream_arr_set(dplink_siso_arr, dp_ready, 'READY')

Use c_sdp_bdo_reorder_nof_blocks_max = 4 to save block RAM. Ensure c_sdp_bdo_reorder_nof_blocks_max <= nof_bdo_destinations_max in revision. Choose nof_bdo_destinations_max = 8.

Use g_use_tech_jesd204b_v2 as generic instead of internal constant, to allow different selection in designs.

Add debug signals. Correct single cycle rxlink_sysref. Correct FIFO data width to c_jesd204b_rx_framer_data_w.

restructured rdma_packetiser_assemble_header and created

Closes HPR-148

See merge request !380

eth_ip_offload_tx. Also added rdma_packetiser

RTSD-225: Update technology_name for Agilex 7 from xxxx to the expected delivered iWave platform.

Closes RTSD-225

See merge request !378

RTSD-225: Renamed technology part agi027_xxxx into agi027_1e1v and Agi027_xxxx into Agi027_1e1v, the last four characters of the expected delivered type part, so 'xxxx = 1e1v'

RTSD-181: Continuation of porting RAM for Intel Agilex 7

Closes RTSD-181

See merge request !376