Merge branch 'master' of git.astron.nl:rtsd/hdl

libraries/base/common/src/vhdl/common_paged_ram_cr_cw.vhd

@@ -40,7 +40,7 @@
 -- . The crw_crw RAM covers all other variants, which were utilized by other
 --   common RAM variant files. However, because the crw_crw IP is no longer
 --   supported as it was previously used for previous FPGA technology identifiers
---   (device types) by the Agilex 7 (agi027_xxxx), the individual IPs should be
+--   (device types) by the Agilex 7 (agi027_1e1v), the individual IPs should be
 --   used. As a result, this file has been created. [1]
 -- Reference:
 --   [1] Based on the architecture of common_paged_ram_crw_crw.vhd.

libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd

 -- -----------------------------------------------------------------------------
 --
--- Copyright 2011-2023
+-- Copyright 2011-2024
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
@@ -38,8 +38,8 @@
 --   pages are then mapped at subsequent addresses in the buf RAM.
 -- . The "use_adr" variant is optimal for speed, so that is set as default.
 -- Issues:
---   Unavailable for Intel Agilex 7 (agi027_xxxx). See common_paged_ram_rw_rw
---   for more context.
+--   Dual clock support is unavailable for Intel Agilex 7 (agi027_1e1v).
+--   See common_paged_ram_rw_rw for more context.
 
 library IEEE, technology_lib;
 use IEEE.std_logic_1164.all;

libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd

@@ -41,7 +41,7 @@
 -- . The crw_crw RAM covers all other variants, which were utilized by other
 --   common RAM variant files. However, because the crw_crw IP is no longer
 --   supported as it was previously used for previous FPGA technology identifiers
---   (device types) by the Agilex 7 (agi027_xxxx), the rw_rw IP should be used.
+--   (device types) by the Agilex 7 (agi027_1e1v), the rw_rw IP should be used.
 --   As a result, this file has been modified. [1]
 -- Reference:
 --   [1] Based on the architecture of common_paged_ram_crw_crw.vhd.

libraries/base/common/src/vhdl/common_ram_cr_cw.vhd

@@ -30,7 +30,7 @@
 --   The crw_crw RAM covers all other variants, which were utilized by other
 --   common RAM variant files. However, because the crw_crw IP is no longer
 --   supported as it was previously used for previous FPGA technology identifiers
---   (device types) by the Agilex 7 (agi027_xxxx), the individual IPs should be
+--   (device types) by the Agilex 7 (agi027_1e1v), the individual IPs should be
 --   used. As a result, this file has been modified. [1]
 -- Reference:
 --   [1] Based on the architecture of common_ram_crw_crw.vhd.

libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd

@@ -25,7 +25,7 @@
 --   Use port a only for write in write clock domain
 --   Use port b only for read in read clock domain
 -- Remark:
---   Because the Agilex 7 (agi027_xxxx) does not support the crwk_crw IP,
+--   Because the Agilex 7 (agi027_1e1v) does not support the crwk_crw IP,
 --   and unfortunately, the rwk_rw IP isn't supported either, the crk_cw IP
 --   has been created, resulting in modifications to this file.[1]
 -- Reference:

libraries/base/common/src/vhdl/common_ram_crw_cr.vhd

@@ -23,8 +23,8 @@
 -- Changed by:
 --   D.F. Brouwer
 -- Issues:
---   Unavailable for Intel Agilex 7 (agi027_xxxx). See common_ram_rw_rw
---   for more context.
+--   Dual clock support is unavailable for Intel Agilex 7 (agi027_1e1v).
+--   See common_ram_rw_rw for more context.
 
 library IEEE, technology_lib;
 use IEEE.std_logic_1164.all;

libraries/base/common/src/vhdl/common_ram_crw_crw.vhd

 -- -----------------------------------------------------------------------------
 --
--- Copyright 2014-2023
+-- Copyright 2014-2024
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
@@ -23,8 +23,8 @@
 -- Changed by:
 --   D.F. Brouwer
 -- Issues:
---   Unavailable for Intel Agilex 7 (agi027_xxxx). See common_ram_rw_rw
---   for more context.
+--   Dual clock support is unavailable for Intel Agilex 7 (agi027_1e1v).
+--   See common_ram_rw_rw for more context.
 
 library IEEE, technology_lib, tech_memory_lib;
 use IEEE.std_logic_1164.all;

libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd

 -- -----------------------------------------------------------------------------
 --
--- Copyright 2014-2023
+-- Copyright 2014-2024
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
@@ -23,8 +23,8 @@
 -- Changed by:
 --   D.F. Brouwer
 -- Issues:
---   Unavailable for Intel Agilex 7 (agi027_xxxx). See common_ram_cr_cw_ratio
---   for more context.
+--   Dual clock and ratio support is unavailable for Intel Agilex 7 (agi027_1e1v).
+--   See common_ram_cr_cw_ratio for more context.
 
 library IEEE, technology_lib, tech_memory_lib;
 use IEEE.std_logic_1164.all;

libraries/base/common/src/vhdl/common_ram_crw_cw.vhd

 -- -----------------------------------------------------------------------------
 --
--- Copyright 2014-2023
+-- Copyright 2014-2024
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
@@ -23,8 +23,8 @@
 -- Changed by:
 --   D.F. Brouwer
 -- Issues:
---   Unavailable for Intel Agilex 7 (agi027_xxxx). See common_ram_rw_rw
---   for more context.
+--   Dual clock support is unavailable for Intel Agilex 7 (agi027_1e1v).
+--   See common_ram_rw_rw for more context.
 
 library IEEE, technology_lib;
 use IEEE.std_logic_1164.all;

libraries/base/common/src/vhdl/common_ram_rw_rw.vhd

@@ -28,7 +28,7 @@
 --   The crw_crw RAM covers all other variants, which were utilized by other
 --   common RAM variant files. However, because the crw_crw IP is no longer
 --   supported as it was previously used for previous FPGA technology identifiers
---   (device types) by the Agilex 7 (agi027_xxxx), the rw_rw IP should be used.
+--   (device types) by the Agilex 7 (agi027_1e1v), the rw_rw IP should be used.
 --   As a result, this file has been modified. [1]
 -- Reference:
 --   [1] Based on the architecture of common_ram_crw_crw.vhd.

libraries/dsp/st/src/vhdl/st_sst.vhd

@@ -89,7 +89,7 @@ architecture str of st_sst is
   constant c_nof_stat_w   : natural := ceil_log2(g_nof_stat);
   constant c_nof_word     : natural := g_stat_data_sz * g_nof_stat;
   constant c_nof_word_w   : natural := ceil_log2(c_nof_word);
-  constant g_stat_word_w  : natural := g_stat_data_sz * c_word_w;
+  constant c_stat_word_w  : natural := g_stat_data_sz * c_word_w;
   constant zeros          : std_logic_vector(c_nof_stat_w - 1 downto 0) := (others => '0');
 
   -- Statistics register
@@ -100,7 +100,7 @@ architecture str of st_sst is
                                         init_sl  => '0');  -- MM side : sla_in, sla_out
   constant c_stat_ram     : t_c_mem := (latency  => 1,
                                         adr_w    => c_nof_stat_w,
-                                        dat_w    => g_stat_word_w,
+                                        dat_w    => c_stat_word_w,
                                         nof_dat  => g_nof_stat,
                                         init_sl  => '0');  -- ST side : stat_mosi
 

libraries/dsp/wpfb/quartus_iwave/README.txt

@@ -38,7 +38,7 @@ Contents:
 
   To investigate the resource usage, timing reports with fmax summary and time critical
   paths by synthesis of the Subband Filterbank (wpfb_unit_dev.vhd) for the Agilex 7
-  (agi027_xxxx) FPGA with buildset iwave.
+  (agi027_1e1v) FPGA with buildset iwave.
 
 
 2) Description 

libraries/dsp/wpfb/quartus_iwave/alma/hdllib.cfg

@@ -2,7 +2,7 @@ hdl_lib_name = iwave_synthesis_wpfb_alma
 hdl_library_clause_name = iwave_synthesis_wpfb_alma_lib
 hdl_lib_uses_synth = common diag dp fft filter mm pft2 pfb2 rTwoSDF si st wpfb
 hdl_lib_uses_sim = 
-hdl_lib_technology = ip_agi027_xxxx
+hdl_lib_technology = ip_agi027_1e1v
 
 synth_files = 
     iwave_synthesis_wpfb_alma.vhd

libraries/dsp/wpfb/quartus_iwave/alma/iwave_synthesis_wpfb_alma.vhd

@@ -25,7 +25,7 @@
 -- Purpose:
 -- . Wrapper for wpfb (wideband polyphase filterbank with ports for subband 
 --   statistics and streaming interfaces) synthesis design for iwave Agilex 7
---   (c_tech_agi027_xxxx).
+--   (c_tech_agi027_1e1v).
 -- . Implements the functionality of the subband filterbank (Fsub) using the 
 --   ALMA design parameters. 
 -- Description:

libraries/dsp/wpfb/quartus_iwave/lofar2/hdllib.cfg

@@ -2,7 +2,7 @@ hdl_lib_name = iwave_synthesis_wpfb_lofar2
 hdl_library_clause_name = iwave_synthesis_wpfb_lofar2_lib
 hdl_lib_uses_synth = common diag dp fft filter mm pft2 pfb2 rTwoSDF si st wpfb
 hdl_lib_uses_sim = 
-hdl_lib_technology = ip_agi027_xxxx
+hdl_lib_technology = ip_agi027_1e1v
 
 synth_files = 
     iwave_synthesis_wpfb_lofar2.vhd

libraries/dsp/wpfb/quartus_iwave/lofar2/iwave_synthesis_wpfb_lofar2.vhd

@@ -25,7 +25,7 @@
 -- Purpose:
 -- . Wrapper for wpfb (wideband polyphase filterbank with ports for subband 
 --   statistics and streaming interfaces) synthesis design for iwave Agilex 7
---   (c_tech_agi027_xxxx).
+--   (c_tech_agi027_1e1v).
 -- . Implements the functionality of the subband filterbank (Fsub) using the 
 --   LOFAR2 design parameters. 
 -- Description:

libraries/technology/fifo/hdllib.cfg

 hdl_lib_name = tech_fifo
 hdl_library_clause_name = tech_fifo_lib
-hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo ip_arria10_e1sg_fifo ip_arria10_e2sg_fifo ip_ultrascale_fifo ip_agi027_xxxx_fifo
+hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo ip_arria10_e1sg_fifo ip_arria10_e2sg_fifo ip_ultrascale_fifo ip_agi027_1e1v_fifo
 hdl_lib_uses_sim = 
 hdl_lib_technology = 
 hdl_lib_disclose_library_clause_names =
@@ -10,7 +10,7 @@ hdl_lib_disclose_library_clause_names =
     ip_arria10_e1sg_fifo   ip_arria10_e1sg_fifo_lib
     ip_arria10_e2sg_fifo   ip_arria10_e2sg_fifo_lib
     ip_ultrascale_fifo     ip_arria10_ultrascale_lib
-    ip_agi027_xxxx_fifo    ip_agi027_xxxx_fifo_lib
+    ip_agi027_1e1v_fifo    ip_agi027_1e1v_fifo_lib
 
 synth_files =
     tech_fifo_component_pkg.vhd

libraries/technology/fifo/tech_fifo_component_pkg.vhd

@@ -416,10 +416,10 @@ package tech_fifo_component_pkg is
   end component;
 
   -----------------------------------------------------------------------------
-  -- ip_agi027_xxxx
+  -- ip_agi027_1e1v
   -----------------------------------------------------------------------------
 
-  component ip_agi027_xxxx_fifo_sc is
+  component ip_agi027_1e1v_fifo_sc is
   generic (
     g_use_eab   : string := "ON";
     g_dat_w     : natural := 20;
@@ -438,7 +438,7 @@ package tech_fifo_component_pkg is
   );
   end component;
 
-  component ip_agi027_xxxx_fifo_dc is
+  component ip_agi027_1e1v_fifo_dc is
   generic (
     g_use_eab   : string := "ON";
     g_dat_w     : natural := 20;
@@ -459,7 +459,7 @@ package tech_fifo_component_pkg is
   );
   end component;
 
-  component ip_agi027_xxxx_fifo_dc_mixed_widths is
+  component ip_agi027_1e1v_fifo_dc_mixed_widths is
   generic (
     g_nof_words : natural := 1024;  -- FIFO size in nof wr_dat words
     g_wrdat_w   : natural := 20;

libraries/technology/fifo/tech_fifo_dc.vhd

@@ -34,7 +34,7 @@ library ip_arria10_e3sge3_fifo_lib;
 library ip_arria10_e1sg_fifo_lib;
 library ip_arria10_e2sg_fifo_lib;
 library ip_ultrascale_fifo_lib;
-library ip_agi027_xxxx_fifo_lib;
+library ip_agi027_1e1v_fifo_lib;
 
 entity tech_fifo_dc is
   generic (
@@ -96,8 +96,8 @@ begin
     port map (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
   end generate;
 
-  gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
-    u0 : ip_agi027_xxxx_fifo_dc
+  gen_ip_agi027_1e1v : if g_technology = c_tech_agi027_1e1v generate
+    u0 : ip_agi027_1e1v_fifo_dc
     generic map (g_use_eab, g_dat_w, g_nof_words)
     port map (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
   end generate;

libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd

@@ -34,7 +34,7 @@ library ip_arria10_e3sge3_fifo_lib;
 library ip_arria10_e1sg_fifo_lib;
 library ip_arria10_e2sg_fifo_lib;
 library ip_ultrascale_fifo_lib;
-library ip_agi027_xxxx_fifo_lib;
+library ip_agi027_1e1v_fifo_lib;
 
 entity tech_fifo_dc_mixed_widths is
   generic (
@@ -96,8 +96,8 @@ begin
     port map (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
   end generate;
 
-  gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
-    u0 : ip_agi027_xxxx_fifo_dc_mixed_widths
+  gen_ip_agi027_1e1v : if g_technology = c_tech_agi027_1e1v generate
+    u0 : ip_agi027_1e1v_fifo_dc_mixed_widths
     generic map (g_nof_words, g_wrdat_w, g_rddat_w)
     port map (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
   end generate;