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Commit 21545c33 authored by Eric Kooistra's avatar Eric Kooistra
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Use wr_rst based on core_pll_locked for FIFO.

parent 8a27e9aa
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1 merge request!381rx_clk -> dp_clk FIFO in JESD204b component.
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libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd
+ 18
− 8
View file @ 21545c33
...@@ -117,13 +117,14 @@ architecture str of ip_arria10_e1sg_jesd204b_v2 is ...@@ -117,13 +117,14 @@ architecture str of ip_arria10_e1sg_jesd204b_v2 is
signal pll_reset_arr : std_logic_vector(g_nof_streams - 1 downto 0); signal pll_reset_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal xcvr_rst_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '1'); signal xcvr_rst_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '1');
signal rx_avs_rst_arr : std_logic_vector(g_nof_streams - 1 downto 0); signal rx_avs_rst_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal rx_avs_rst_n_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal rxlink_rst_async_arr : std_logic_vector(g_nof_streams - 1 downto 0); signal rxlink_rst_async_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal rxlink_rst_arr : std_logic_vector(g_nof_streams - 1 downto 0); signal rxlink_rst_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal rxlink_rst : std_logic;
signal rx_avs_rst_n_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal rxlink_rst_n_arr : std_logic_vector(g_nof_streams - 1 downto 0); signal rxlink_rst_n_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal core_pll_locked : std_logic; signal core_pll_locked : std_logic;
signal mm_core_pll_locked : std_logic; signal mm_core_pll_locked : std_logic;
signal wr_core_pll_locked : std_logic;
signal wr_rst : std_logic := '1';
signal rxlink_sysref_1 : std_logic; signal rxlink_sysref_1 : std_logic;
signal rxlink_sysref_2 : std_logic; signal rxlink_sysref_2 : std_logic;
signal rxlink_sysref_3 : std_logic; signal rxlink_sysref_3 : std_logic;
...@@ -483,9 +484,6 @@ begin ...@@ -483,9 +484,6 @@ begin
end process; end process;
end generate; -- gen_jesd204b_rx_channels : for I in 0 to g_nof_streams-1 generate end generate; -- gen_jesd204b_rx_channels : for I in 0 to g_nof_streams-1 generate
-- Combine into single reset
rxlink_rst <= vector_or(rxlink_rst_arr) when rising_edge(rxlink_clk);
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Cross from 100 MHz rxlink_clk domain to 200MHz dp_clk domain using a FIFO -- Cross from 100 MHz rxlink_clk domain to 200MHz dp_clk domain using a FIFO
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
...@@ -494,6 +492,8 @@ begin ...@@ -494,6 +492,8 @@ begin
-- control the FIFO uses src_in_arr(0).ready as read strobe. Using only input (0) is -- control the FIFO uses src_in_arr(0).ready as read strobe. Using only input (0) is
-- possible, because all snk_in_arr() inputs will have same ctrl and info when Rx -- possible, because all snk_in_arr() inputs will have same ctrl and info when Rx
-- JESD204B IP is synchronized. -- JESD204B IP is synchronized.
wr_rst <= not wr_core_pll_locked;
u_dp_fifo_dc_arr : entity dp_lib.dp_fifo_dc_arr u_dp_fifo_dc_arr : entity dp_lib.dp_fifo_dc_arr
generic map ( generic map (
g_nof_streams => g_nof_streams, g_nof_streams => g_nof_streams,
...@@ -504,7 +504,7 @@ begin ...@@ -504,7 +504,7 @@ begin
g_fifo_size => c_fifo_size g_fifo_size => c_fifo_size
) )
port map ( port map (
wr_rst => rxlink_rst, wr_rst => wr_rst,
wr_clk => rxlink_clk, wr_clk => rxlink_clk,
rd_rst => dp_rst, rd_rst => dp_rst,
rd_clk => dp_clk, rd_clk => dp_clk,
...@@ -514,7 +514,6 @@ begin ...@@ -514,7 +514,6 @@ begin
src_out_arr => dplink_sosi_arr src_out_arr => dplink_sosi_arr
); );
dplink_siso_arr <= func_dp_stream_arr_set(dplink_siso_arr, dp_ready, "READY"); dplink_siso_arr <= func_dp_stream_arr_set(dplink_siso_arr, dp_ready, "READY");
-- The dp_clk at 200 MHz and rxlink_clk at 100 MHz are locked to same reference. -- The dp_clk at 200 MHz and rxlink_clk at 100 MHz are locked to same reference.
...@@ -601,7 +600,18 @@ begin ...@@ -601,7 +600,18 @@ begin
); );
end generate; end generate;
u_common_areset_pll_locked : entity common_lib.common_areset u_common_areset_wr_core_pll_locked : entity common_lib.common_areset
generic map (
g_in_rst_level => '0', -- synchronises the rising edge of input in_rst.
g_rst_level => '0'
)
port map (
in_rst => core_pll_locked,
clk => rxlink_clk,
out_rst => wr_core_pll_locked
);
u_common_areset_mm_core_pll_locked : entity common_lib.common_areset
generic map ( generic map (
g_in_rst_level => '0', -- synchronises the rising edge of input in_rst. g_in_rst_level => '0', -- synchronises the rising edge of input in_rst.
g_rst_level => '0' g_rst_level => '0'
......
libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd
+ 18
− 8
View file @ 21545c33
...@@ -117,13 +117,14 @@ architecture str of ip_arria10_e2sg_jesd204b_v2 is ...@@ -117,13 +117,14 @@ architecture str of ip_arria10_e2sg_jesd204b_v2 is
signal pll_reset_arr : std_logic_vector(g_nof_streams - 1 downto 0); signal pll_reset_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal xcvr_rst_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '1'); signal xcvr_rst_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '1');
signal rx_avs_rst_arr : std_logic_vector(g_nof_streams - 1 downto 0); signal rx_avs_rst_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal rx_avs_rst_n_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal rxlink_rst_async_arr : std_logic_vector(g_nof_streams - 1 downto 0); signal rxlink_rst_async_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal rxlink_rst_arr : std_logic_vector(g_nof_streams - 1 downto 0); signal rxlink_rst_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal rxlink_rst : std_logic;
signal rx_avs_rst_n_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal rxlink_rst_n_arr : std_logic_vector(g_nof_streams - 1 downto 0); signal rxlink_rst_n_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal core_pll_locked : std_logic; signal core_pll_locked : std_logic;
signal mm_core_pll_locked : std_logic; signal mm_core_pll_locked : std_logic;
signal wr_core_pll_locked : std_logic;
signal wr_rst : std_logic := '1';
signal rxlink_sysref_1 : std_logic; signal rxlink_sysref_1 : std_logic;
signal rxlink_sysref_2 : std_logic; signal rxlink_sysref_2 : std_logic;
signal rxlink_sysref_3 : std_logic; signal rxlink_sysref_3 : std_logic;
...@@ -483,9 +484,6 @@ begin ...@@ -483,9 +484,6 @@ begin
end process; end process;
end generate; -- gen_jesd204b_rx_channels : for I in 0 to g_nof_streams-1 generate end generate; -- gen_jesd204b_rx_channels : for I in 0 to g_nof_streams-1 generate
-- Combine into single reset
rxlink_rst <= vector_or(rxlink_rst_arr) when rising_edge(rxlink_clk);
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Cross from 100 MHz rxlink_clk domain to 200MHz dp_clk domain using a FIFO -- Cross from 100 MHz rxlink_clk domain to 200MHz dp_clk domain using a FIFO
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
...@@ -494,6 +492,8 @@ begin ...@@ -494,6 +492,8 @@ begin
-- control the FIFO uses src_in_arr(0).ready as read strobe. Using only input (0) is -- control the FIFO uses src_in_arr(0).ready as read strobe. Using only input (0) is
-- possible, because all snk_in_arr() inputs will have same ctrl and info when Rx -- possible, because all snk_in_arr() inputs will have same ctrl and info when Rx
-- JESD204B IP is synchronized. -- JESD204B IP is synchronized.
wr_rst <= not wr_core_pll_locked;
u_dp_fifo_dc_arr : entity dp_lib.dp_fifo_dc_arr u_dp_fifo_dc_arr : entity dp_lib.dp_fifo_dc_arr
generic map ( generic map (
g_nof_streams => g_nof_streams, g_nof_streams => g_nof_streams,
...@@ -504,7 +504,7 @@ begin ...@@ -504,7 +504,7 @@ begin
g_fifo_size => c_fifo_size g_fifo_size => c_fifo_size
) )
port map ( port map (
wr_rst => rxlink_rst, wr_rst => wr_rst,
wr_clk => rxlink_clk, wr_clk => rxlink_clk,
rd_rst => dp_rst, rd_rst => dp_rst,
rd_clk => dp_clk, rd_clk => dp_clk,
...@@ -514,7 +514,6 @@ begin ...@@ -514,7 +514,6 @@ begin
src_out_arr => dplink_sosi_arr src_out_arr => dplink_sosi_arr
); );
dplink_siso_arr <= func_dp_stream_arr_set(dplink_siso_arr, dp_ready, "READY"); dplink_siso_arr <= func_dp_stream_arr_set(dplink_siso_arr, dp_ready, "READY");
-- The dp_clk at 200 MHz and rxlink_clk at 100 MHz are locked to same reference. -- The dp_clk at 200 MHz and rxlink_clk at 100 MHz are locked to same reference.
...@@ -601,7 +600,18 @@ begin ...@@ -601,7 +600,18 @@ begin
); );
end generate; end generate;
u_common_areset_pll_locked : entity common_lib.common_areset u_common_areset_wr_core_pll_locked : entity common_lib.common_areset
generic map (
g_in_rst_level => '0', -- synchronises the rising edge of input in_rst.
g_rst_level => '0'
)
port map (
in_rst => core_pll_locked,
clk => rxlink_clk,
out_rst => wr_core_pll_locked
);
u_common_areset_mm_core_pll_locked : entity common_lib.common_areset
generic map ( generic map (
g_in_rst_level => '0', -- synchronises the rising edge of input in_rst. g_in_rst_level => '0', -- synchronises the rising edge of input in_rst.
g_rst_level => '0' g_rst_level => '0'
......
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