Apply dp_ready FIFO flow control in generate loop, instead of using...

Apply dp_ready FIFO flow control in generate loop, instead of using func_dp_stream_arr_set(dplink_siso_arr, dp_ready, 'READY')

libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd

@@ -98,6 +98,8 @@ architecture str of ip_arria10_e1sg_jesd204b_v2 is
   signal reset_seq_miso_arr         : t_mem_miso_arr(g_nof_streams - 1 downto 0) := (others => c_mem_miso_rst);
 
   -- Clocks
+  -- . The 200MHz rxframe_clk is not used in v2, the constraints on the PLL output frame_clk in
+  --   lofar2_unb2c_sdp_station.sdc will be ingored by Quartus.
   signal rxframe_clk                : std_logic;
   signal rxlink_clk                 : std_logic;
   signal jesd204b_avs_clk           : std_logic;
@@ -299,7 +301,7 @@ begin
   dp_sosi <= i_dp_sosi_arr(0);
 
   -- The mm_rst resets the MM interface, but is also used to reset the JESD IP reset sequencer.
-  -- Therefore a reset of mm_rst effectively resets the entire ip_arria10_e1sg_jesd204b.
+  -- Therefore a reset of mm_rst effectively resets the entire JESD IP.
 
   -- The avs clock is driven by the rxlink_clk for simulation. This is a workaround for a bug
   -- in the Q18.0 IP where the jesd receiver fails to recognize the SYSREF pulse
@@ -482,6 +484,10 @@ begin
           end if;
         end if;
       end process;
+
+      -- Apply toggling ready control for cross 100 MHz rxlink_clk domain to 200MHz dp_clk domain
+      -- u_dp_fifo_dc_arr FIFO.
+      dplink_siso_arr(i).ready <= dp_ready;
     end generate;  -- gen_jesd204b_rx_channels : for I in 0 to g_nof_streams-1 generate
 
     -----------------------------------------------------------------------------
@@ -514,8 +520,6 @@ begin
         src_out_arr      => dplink_sosi_arr
       );
 
-    dplink_siso_arr <= func_dp_stream_arr_set(dplink_siso_arr, dp_ready, "READY");
-
     -- The dp_clk at 200 MHz and rxlink_clk at 100 MHz are locked to same reference.
     -- Toggle dp_index every dp_clk cycle to have the same read rate in dp_clk domain,
     -- as the write rate in rxlink_clk domain.

libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd

@@ -98,6 +98,8 @@ architecture str of ip_arria10_e2sg_jesd204b_v2 is
   signal reset_seq_miso_arr         : t_mem_miso_arr(g_nof_streams - 1 downto 0) := (others => c_mem_miso_rst);
 
   -- Clocks
+  -- . The 200MHz rxframe_clk is not used in v2, the constraints on the PLL output frame_clk in
+  --   lofar2_unb2c_sdp_station.sdc will be ingored by Quartus.
   signal rxframe_clk                : std_logic;
   signal rxlink_clk                 : std_logic;
   signal jesd204b_avs_clk           : std_logic;
@@ -299,7 +301,7 @@ begin
   dp_sosi <= i_dp_sosi_arr(0);
 
   -- The mm_rst resets the MM interface, but is also used to reset the JESD IP reset sequencer.
-  -- Therefore a reset of mm_rst effectively resets the entire ip_arria10_e2sg_jesd204b.
+  -- Therefore a reset of mm_rst effectively resets the entire JESD IP.
 
   -- The avs clock is driven by the rxlink_clk for simulation. This is a workaround for a bug
   -- in the Q18.0 IP where the jesd receiver fails to recognize the SYSREF pulse
@@ -482,6 +484,10 @@ begin
           end if;
         end if;
       end process;
+
+      -- Apply toggling ready control for cross 100 MHz rxlink_clk domain to 200MHz dp_clk domain
+      -- u_dp_fifo_dc_arr FIFO.
+      dplink_siso_arr(i).ready <= dp_ready;
     end generate;  -- gen_jesd204b_rx_channels : for I in 0 to g_nof_streams-1 generate
 
     -----------------------------------------------------------------------------
@@ -514,8 +520,6 @@ begin
         src_out_arr      => dplink_sosi_arr
       );
 
-    dplink_siso_arr <= func_dp_stream_arr_set(dplink_siso_arr, dp_ready, "READY");
-
     -- The dp_clk at 200 MHz and rxlink_clk at 100 MHz are locked to same reference.
     -- Toggle dp_index every dp_clk cycle to have the same read rate in dp_clk domain,
     -- as the write rate in rxlink_clk domain.