Make equivalent to ip_arria10_e2sg_jesd204b.vhd

libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd

@@ -125,11 +125,22 @@ architecture str of ip_arria10_e1sg_jesd204b is
   signal rxlink_sysref_2            : std_logic;
   signal rxframe_sysref_1           : std_logic;
   signal rxframe_sysref_2           : std_logic;
+  signal i_rx_src_out_arr           : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+  -- debug signal used to view input 0 in Wave Window
+  signal rx_src_out                 : t_dp_sosi;
 
   -- Data path
   signal jesd204b_rx_link_data_arr  : std_logic_vector(c_jesd204b_rx_data_w * g_nof_streams - 1 downto 0);
   signal jesd204b_rx_link_valid_arr : std_logic_vector(g_nof_streams - 1 downto 0);
-  signal jesd204b_rx_somf_arr       : std_logic_vector(c_jesd204b_rx_somf_w * g_nof_streams - 1 downto 0);
+  signal jesd204b_rx_link_somf_arr  : std_logic_vector(c_jesd204b_rx_somf_w * g_nof_streams - 1 downto 0);
+  -- debug signal to view input 0 in Wave Window
+  signal jesd204b_rx_link_data      : std_logic_vector(c_jesd204b_rx_data_w - 1 downto 0);
+  signal jesd204b_rx_link_data_hi   : std_logic_vector(c_jesd204b_rx_framer_data_w - 1 downto 0);
+  signal jesd204b_rx_link_data_lo   : std_logic_vector(c_jesd204b_rx_framer_data_w - 1 downto 0);
+  signal jesd204b_rx_link_valid     : std_logic;
+  signal jesd204b_rx_link_somf      : std_logic_vector(c_jesd204b_rx_somf_w - 1 downto 0);
+  signal jesd204b_rx_link_somf_hi   : std_logic_vector(c_jesd204b_rx_framer_somf_w - 1 downto 0);
+  signal jesd204b_rx_link_somf_lo   : std_logic_vector(c_jesd204b_rx_framer_somf_w - 1 downto 0);
 
   -- outputs to control ADC initialization/syncronization phase
   signal jesd204b_sync_n_internal_arr   : std_logic_vector(g_nof_streams - 1 downto 0);
@@ -236,6 +247,17 @@ architecture str of ip_arria10_e1sg_jesd204b is
     );
   end component ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12;
 begin
+  -- Debug signals to view input 0 in Wave Window
+  jesd204b_rx_link_data <= jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w - 1 downto 0);
+  jesd204b_rx_link_data_hi <= jesd204b_rx_link_data(c_jesd204b_rx_data_w - 1 downto c_jesd204b_rx_framer_data_w);
+  jesd204b_rx_link_data_lo <= jesd204b_rx_link_data(c_jesd204b_rx_framer_data_w - 1 downto 0);
+  jesd204b_rx_link_valid <= jesd204b_rx_link_valid_arr(0);
+  jesd204b_rx_link_somf <= jesd204b_rx_link_somf_arr(c_jesd204b_rx_somf_w - 1 downto 0);
+  jesd204b_rx_link_somf_hi <= jesd204b_rx_link_somf(c_jesd204b_rx_somf_w - 1 downto c_jesd204b_rx_framer_somf_w);
+  jesd204b_rx_link_somf_lo <= jesd204b_rx_link_somf(c_jesd204b_rx_framer_somf_w - 1 downto 0);
+  rx_src_out_arr <= i_rx_src_out_arr;
+  rx_src_out <= i_rx_src_out_arr(0);
+
   -- The mm_rst resets the MM interface, but is also used to reset the JESD IP reset sequencer.
   -- Therefore a reset of mm_rst effectively resets the entire ip_arria10_e1sg_jesd204b and
   -- causes a reset on the rx_rst output.
@@ -307,8 +329,8 @@ begin
           rxlink_rst_n_reset_n       => rxlink_rst_n_arr(i),  -- Assoc with rxlink_clk (Intel JESD204B-UG p69)
           rxphy_clk                  => OPEN,  -- Not used in Subclass 0 (Intel JESD204B-UG p63)
           sof                        => OPEN,
-          somf                       => jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1
-                                                      downto c_jesd204b_rx_somf_w * i),
+          somf                       => jesd204b_rx_link_somf_arr(c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1
+                                                           downto c_jesd204b_rx_somf_w * i),
           sysref                     => rxlink_sysref_2
         );
 
@@ -395,31 +417,33 @@ begin
       begin
         if rising_edge(rxframe_clk) then
           if rxframe_rst_n_arr(i) = '0' then
-            rx_src_out_arr(i).data <= (others => '0');
-            rx_src_out_arr(i).channel <= (others => '0');
+            i_rx_src_out_arr(i).data <= (others => '0');
+            i_rx_src_out_arr(i).channel <= (others => '0');
+            i_rx_src_out_arr(i).valid <= '0';
             rxframe_toggle_arr(i) <= '0';
-            rx_src_out_arr(i).valid <= '0';
           else
-            rx_src_out_arr(i).valid <= jesd204b_rx_link_valid_arr(i);
             if jesd204b_rx_link_valid_arr(i) = '0' then
-              rx_src_out_arr(i).data <= (others => '0');
-              rx_src_out_arr(i).channel <= (others => '0');
+              i_rx_src_out_arr(i).data <= (others => '0');
+              i_rx_src_out_arr(i).channel <= (others => '0');
+              i_rx_src_out_arr(i).valid <= '0';
+              rxframe_toggle_arr(i) <= '0';
             else
               if rxframe_toggle_arr(i) = '1' then
-                rx_src_out_arr(i).data <= RESIZE_DP_SDATA(jesd204b_rx_link_data_arr(
-                                          c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w - 1 downto
-                                          c_jesd204b_rx_data_w * i));
-                rx_src_out_arr(i).channel <= RESIZE_DP_CHANNEL(jesd204b_rx_somf_arr(
-                                             c_jesd204b_rx_somf_w * i + c_jesd204b_rx_framer_somf_w - 1 downto
-                                             c_jesd204b_rx_somf_w * i));
+                i_rx_src_out_arr(i).data <= RESIZE_DP_SDATA(jesd204b_rx_link_data_arr(
+                                            c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w - 1 downto
+                                            c_jesd204b_rx_data_w * i));
+                i_rx_src_out_arr(i).channel <= RESIZE_DP_CHANNEL(jesd204b_rx_link_somf_arr(
+                                               c_jesd204b_rx_somf_w * i + c_jesd204b_rx_framer_somf_w - 1 downto
+                                               c_jesd204b_rx_somf_w * i));
               else
-                rx_src_out_arr(i).data <= RESIZE_DP_SDATA(jesd204b_rx_link_data_arr(
-                                          c_jesd204b_rx_data_w * i + c_jesd204b_rx_data_w - 1 downto
-                                          c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w));
-                rx_src_out_arr(i).channel <= RESIZE_DP_CHANNEL(jesd204b_rx_somf_arr(
-                                             c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1 downto
-                                             c_jesd204b_rx_somf_w * i + c_jesd204b_rx_framer_somf_w));
+                i_rx_src_out_arr(i).data <= RESIZE_DP_SDATA(jesd204b_rx_link_data_arr(
+                                            c_jesd204b_rx_data_w * i + c_jesd204b_rx_data_w - 1 downto
+                                            c_jesd204b_rx_data_w * i + c_jesd204b_rx_framer_data_w));
+                i_rx_src_out_arr(i).channel <= RESIZE_DP_CHANNEL(jesd204b_rx_link_somf_arr(
+                                               c_jesd204b_rx_somf_w * i + c_jesd204b_rx_somf_w - 1 downto
+                                               c_jesd204b_rx_somf_w * i + c_jesd204b_rx_framer_somf_w));
               end if;
+              i_rx_src_out_arr(i).valid <= '1';
               rxframe_toggle_arr(i) <= not rxframe_toggle_arr(i);
             end if;
           end if;