processed review comments

applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser.vhd

@@ -59,8 +59,7 @@ entity rdma_packetiser is
     src_in             : in  t_dp_siso := c_dp_siso_rdy;
 
     block_len          : in  std_logic_vector(c_halfword_w - 1 downto 0) -- in octets
-
-   );
+  );
 end rdma_packetiser;
 
 architecture str of rdma_packetiser is

applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_assemble_header.vhd

@@ -420,7 +420,6 @@ begin
   port map (
     rst => st_rst,
     clk => st_clk,
-    snk_out => open,
     snk_in  => snk_in,
     src_out => dp_pipeline_src_out
   );