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Commit 5d724a86 authored by Eric Kooistra's avatar Eric Kooistra
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Add debug signals. Correct single cycle rxlink_sysref. Correct FIFO data width... 

Add debug signals. Correct single cycle rxlink_sysref. Correct FIFO data width to c_jesd204b_rx_framer_data_w.
parent 8fbd7dc7
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1 merge request!381rx_clk -> dp_clk FIFO in JESD204b component.
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