Commits · 936dba67ff3d9103b82f9c5dec527024f3ec90c4 · RTSD / HDL · GitLab

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May 15, 2023
- Add comment about sim_ddr size. · 936dba67
  Eric Kooistra authored 2 years ago
  
  936dba67
May 11, 2023
- Define ddr_gigabytes as integer to be able to represent both > 1GB (HW) and < 1GB (sim) sizes. · aac5f892
  Eric Kooistra authored 2 years ago
  
  aac5f892
Mar 21, 2023
- Add and verify ctlr_nof_bytes_per_word field in reg_io_ddr. · c37576fd
  Eric Kooistra authored 2 years ago
  
  c37576fd
- Add and verify ddr_gigabytes field in reg_io_ddr. · 71e29da7
  Eric Kooistra authored 2 years ago
  
  71e29da7
Mar 20, 2023
- Add c_tech_ddr4_16g_1600m_64, c_tech_ddr4_16g_1600m_72_64 options. · 590e7fd3
  Eric Kooistra authored 2 years ago
  
  590e7fd3
Jan 19, 2022
- Fix simulating DDR4 for unb2c, except for fverifying the dbg_rd_data. · 5174b894
  Eric Kooistra authored 3 years ago
  
  5174b894
- Work around for verifying DDR4 on unb2c. · ae27c70e
  Eric Kooistra authored 3 years ago
  
  ae27c70e
Jul 31, 2018
- fixed the FIXME in io_ddr testbench · f9e6bc4b
  Reinier van der Walle authored 6 years ago
  
  f9e6bc4b
Jul 30, 2018
- placed u_sim_model under gen_ddr3 such that it will not be used for DDR4... · d2c123fa
  Reinier van der Walle authored 6 years ago
  d2c123fa
Jun 13, 2017
- Fixed DDR simulation model. · a2f529f6
  Eric Kooistra authored 8 years ago
  
  a2f529f6
Mar 17, 2017
- Added proc_common_timeout_failure(). · d52574e6
  Eric Kooistra authored 8 years ago
  
  d52574e6
May 11, 2016
- Use tb_end signal. · 5787dd18
  Eric Kooistra authored 9 years ago
  
  5787dd18
Jun 30, 2015
- Removed clock period generics. Corrected c_ctlr_ref_clk_period = 25 MHz for DDR4. · 43931c4b
  Eric Kooistra authored 9 years ago
  
  43931c4b
Jun 26, 2015
- Derive g_rd_fifo_af_margin internally in io_ddr.vhd based on g_tech_ddr.name=DDR3 or DDR4. · 12fd53ea
  Eric Kooistra authored 10 years ago
  
  12fd53ea
Jun 25, 2015
- Used g_cross_domain_delay_len=c_meta_delay_len fixed instead of via generic. · 298065ab
  Eric Kooistra authored 10 years ago
  
  298065ab
Jun 12, 2015
- Added g_sim_model. · 33e83b5a
  Eric Kooistra authored 10 years ago
  
  33e83b5a
Apr 08, 2015
- Removed internal DDR memory model (now needs to be instantiated in tb). Use... · 17ede428
  Eric Kooistra authored 10 years ago
  17ede428
- Removed g_use_ddr_memory_model so the DDR memory model code is not seen/needed... · d51f8638
  Eric Kooistra authored 10 years ago
  d51f8638
- Added missing g_mm_clk_period = 8 ns. · fbd48441
  Eric Kooistra authored 10 years ago
  
  fbd48441
Mar 30, 2015
- Added register map in TB · fc4e910c
  Pepping authored 10 years ago
  
  fc4e910c
Mar 25, 2015
- Renamed g_sim into g_use_ddr_memory_model. · 24cd1054
  Eric Kooistra authored 10 years ago
  
  24cd1054
- Corrected g_sim=>TRUE when external memory model is used. · 6a83e240
  Eric Kooistra authored 10 years ago
  
  6a83e240
Jan 23, 2015
- Defined u_default with typical parameters. · 3519269e
  Eric Kooistra authored 10 years ago
  
  3519269e
- Use g_dp_factor>1 to verify c_rd_fifo_af_margin. · 28b8f1aa
  Eric Kooistra authored 10 years ago
  
  28b8f1aa
- Added g_rd_fifo_depth. · 6ed6463b
  Eric Kooistra authored 10 years ago
  
  6ed6463b
- Added u_wr_burst_size_1. · baf6c23f
  Eric Kooistra authored 10 years ago
  
  baf6c23f
- Improved check on snk_diag_res by placing it after the read FIFO has been read... · 9102d014
  Eric Kooistra authored 10 years ago
  9102d014
Jan 22, 2015
- The DDR4 IP/mem model simulation about 40x slower than that for DDR3. · 1a9bb01b
  Eric Kooistra authored 10 years ago
  
  1a9bb01b
Jan 20, 2015
- Improved stimuli using generics and functions to define the write and read... · 9fed08ae
  Eric Kooistra authored 10 years ago
  9fed08ae
- Improved stimuli using generics and functions to define the write and read block accesses. · b3de752e
  Eric Kooistra authored 10 years ago
  
  b3de752e
Jan 14, 2015
- Define g_tech_ddr as generic. · 5538bc02
  Eric Kooistra authored 10 years ago
  
  5538bc02
Jan 08, 2015
- Added g_sim, when TRUE then use internal DDR memory model in tech_ddr... · e8956d9d
  Eric Kooistra authored 10 years ago
  e8956d9d
- Init dvr_start_address=0 and dvr_nof_data=0. to avoid 'X' after power up. · 22d96617
  Eric Kooistra authored 10 years ago
  
  22d96617
- Wire dvr_done via new dvr_miso.done field instead of via the dvr_miso.waitrequest_n field. · 471d01b1
  Eric Kooistra authored 10 years ago
  
  471d01b1
- Connect dvr_wr_flush_en via dvr_mosi.flush. · 5e468fd4
  Eric Kooistra authored 10 years ago
  
  5e468fd4
- Map original dvr interface signals to dvr_mosi/miso of the record type t_mem_ctlr_mosi/miso. · de3b07b2
  Eric Kooistra authored 10 years ago
  
  de3b07b2
- Check UNSIGNED(wr_fifo_usedw) < c_dp_factor, because a mixed width FIFO cannot... · cb55bd71
  Eric Kooistra authored 10 years ago
  cb55bd71
Jan 07, 2015
- Replaced dvr_end_address by dvr_nof_data. · f77d17f5
  Eric Kooistra authored 10 years ago
  
  f77d17f5
Jan 06, 2015
- Rename dvr_start_addr into dvr_start_address. · aa967f59
  Eric Kooistra authored 10 years ago
  
  aa967f59
- Use ctlr slv address instead of record address. · f9b1a01f
  Eric Kooistra authored 10 years ago
  
  f9b1a01f