Commits · 80100686c99e01af561982f97db2d8632ad9cfd0 · RTSD / HDL · GitLab

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Apr 28, 2016
- Use hdl_lib_uses_ip for the multiple choice IP. · 80100686
  Eric Kooistra authored 9 years ago
  
  80100686
Apr 19, 2016
- Added [section headers]. · b232c8c7
  Eric Kooistra authored 9 years ago
  
  b232c8c7
Mar 11, 2016
- fix duplicate drivers in wrapper · 044030e0
  Jonathan Hargreaves authored 9 years ago
  
  044030e0
Mar 10, 2016
- add ddr4_8g_1600 to packages and wrappers · eecc4c7e
  Jonathan Hargreaves authored 9 years ago
  
  eecc4c7e
Jan 29, 2016
- update technology wrapper to include device e3sge3 for unb2a · 16efe183
  Jonathan Hargreaves authored 9 years ago
  
  16efe183
Oct 12, 2015
- Aligned interfaces · 1509e18f
  Zanting authored 9 years ago
  
  1509e18f
- Aligned interfaces · ffd65ec4
  Zanting authored 9 years ago
  
  ffd65ec4
Oct 01, 2015
- fixed DDR3 IP for 16GB SO-Dimms · aa76980d
  Zanting authored 9 years ago
  
  aa76980d
Sep 30, 2015
- Reverted to own pll/dll for 4g single rank slave · cde216f4
  Zanting authored 9 years ago
  
  cde216f4
- IP for 16GB DDR3 So-Dimm modules added · 878ceca5
  Zanting authored 9 years ago
  
  878ceca5
- IP for 16GB DDR3 So-Dimm modules added · 4750ad20
  Zanting authored 9 years ago
  
  4750ad20
Sep 28, 2015
- IP for 16GB DDR3 So-Dimm modules added · 67c8bcec
  Zanting authored 9 years ago
  
  67c8bcec
Sep 25, 2015
- can choose now ddr4 1600 or 2000 · fda9eccc
  Kenneth Hiemstra authored 9 years ago
  
  fda9eccc
Aug 18, 2015
- added ddr4_4g_2000 IP · 08d9a16e
  Kenneth Hiemstra authored 9 years ago
  
  08d9a16e
Aug 13, 2015
- changed c_tech_ddr4_max to use a dual rank DDR4 as single rank (see · e39ca9bd
  Kenneth Hiemstra authored 9 years ago
  e39ca9bd
- using a dual rank DDR4 but the IP is single rank: disabling 2nd rank by · 0e2b1046
  Kenneth Hiemstra authored 9 years ago
  0e2b1046
Jun 26, 2015
- Improved legenda of cs_w and cs_w_w in table. · 3f0a25a0
  Eric Kooistra authored 9 years ago
  
  3f0a25a0
Jun 24, 2015
- -Removed unused signals and constants. · 588a8417
  Daniel van der Schuur authored 9 years ago
  
  588a8417
- -Changed name of generate and instance name to match entity name to ease wave · d2af806a
  Daniel van der Schuur authored 9 years ago
  d2af806a
Jun 23, 2015
- Default mts=1600 for DDR4 sim models · bf002039
  Eric Kooistra authored 9 years ago
  
  bf002039
- Use dedicated MB ref_clk input instead of via t_tech_ddr4_phy_in. · 109f99ce
  Eric Kooistra authored 9 years ago
  
  109f99ce
Jun 15, 2015
- added the required ref_clk to the IN record for ddr4 · ea595fc2
  Kenneth Hiemstra authored 10 years ago
  
  ea595fc2
Jun 12, 2015
- Moved DDR sim model to sim_ddr.vhd. · 201f8808
  Eric Kooistra authored 10 years ago
  
  201f8808
- Connected cal_ok and cal_fail.diff · c85011f5
  Eric Kooistra authored 10 years ago
  
  c85011f5
- Added c_tech_ddr3_sim_* and c_tech_ddr4_sim_* constants. Added func_tech_sel_ddr() for boolean. · a0a9e860
  Eric Kooistra authored 10 years ago
  
  a0a9e860
Jun 09, 2015
- original func_tech_ddr_ctlr_data_w() function but needs fix for DDR4 · 61aa2a1f
  Kenneth Hiemstra authored 10 years ago
  
  61aa2a1f
Jun 08, 2015
- Moved ip_arria10_ddr4_mem_model_141 library to hdl_lib_uses_sim section. · da9bf9bc
  Eric Kooistra authored 10 years ago
  
  da9bf9bc
Jun 05, 2015
- [temporary fix] for Quartus compilation. Agree on width in · 27875325
  Kenneth Hiemstra authored 10 years ago
  27875325
May 20, 2015
- Updated all IP related files to match Quartus 15.0 which uses libraries with... · 6237fca5
  Eric Kooistra authored 10 years ago
  6237fca5
May 06, 2015
- -Added fast behavioural model to tech_ddr.vhd; · cb21fc96
  Daniel van der Schuur authored 10 years ago
  cb21fc96
May 01, 2015
- ip_stratixiv_ddr3_mem_model only for simulation · 13681134
  Kenneth Hiemstra authored 10 years ago
  
  13681134
Apr 29, 2015
- Fixed connections to single rank memory · ade1b60b
  Zanting authored 10 years ago
  
  ade1b60b
Apr 24, 2015
- Updated c_tech_ddr3_max · a4f69684
  Zanting authored 10 years ago
  
  a4f69684
Apr 22, 2015
- Added DDR3 single rank master and slave · 1188f0b9
  Zanting authored 10 years ago
  
  1188f0b9
- Added DDR3 single rank master and slave · 0b1592e6
  Zanting authored 10 years ago
  
  0b1592e6
Apr 17, 2015
- Moved build_dir_sim and build_dir_synth keys from local hdllib.cfg to central hdltool.cfg · 7053afa9
  Eric Kooistra authored 10 years ago
  
  7053afa9
Apr 08, 2015
- connected cal_ok and fail · d55d0ad2
  Pepping authored 10 years ago
  
  d55d0ad2
- Added array types · 1fcaa2e3
  Pepping authored 10 years ago
  
  1fcaa2e3
- Removed internal DDR memory model (now needs to be instantiated in tb). Use... · 8e1a6162
  Eric Kooistra authored 10 years ago
  8e1a6162
- Removed g_use_ddr_memory_model so the DDR memory model code is not seen/needed... · 7095b485
  Eric Kooistra authored 10 years ago
  7095b485