splitted the terminationcontrol lines from the record types 't_tech_ddr_phy_in' and 't_tech_ddr_phy_ou'

Renamed key hdl_lib_uses into hdl_lib_uses_synth and added new key hdl_lib_uses_sim for extra test_bench_files library dependencies.

Use g_rd_fifo_af_margin to fit one (DDR3 IP) or more (DDR4 IP) rd burst accesses of g_tech_ddr.maxburstsize each.

Improved check on snk_diag_res by placing it after the read FIFO has been read empty. No need for using v_diag_first_rd to ensure that snk_diag_res_val has become 1.

Improved stimuli using generics and functions to define the write and read block accesses. Distinghuis between tests for DDR3 and DDR4, because DDR4 model simulates about 20x slower.

Added g_sim, when TRUE then use internal DDR memory model in tech_ddr component. When FALSE use DDR memory model in test bench.

Only need to reset the state reg, do not reset the other signals to easy timing closure. Use natural for burst_wr_cnt instead of slv.

Define t_mem_ctlr_mosi/miso in common_mem_pkg, to use that instead of the records defined in tech_ddr_pkg. Also remove t_tech_ddr_addr record because it is not needed.

Check UNSIGNED(wr_fifo_usedw) < c_dp_factor, because a mixed width FIFO cannot always be flushed completely empty, which is ok.diff