Commits · 1d8ab1baf1bda6f58821a68ab11cebf3ee687afe · RTSD / HDL · GitLab

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Aug 21, 2023
- RTSD-154 : fix with vhdl_style_fix empty lines 2 · e3e65fb0
  Pieter Donker authored 1 year ago
  
  e3e65fb0
- RTSD-154 : fix with vhdl_style_fix empty lines · f362cb95
  Pieter Donker authored 1 year ago
  
  f362cb95
Aug 16, 2023
- Revert "Merge branch 'RTSD-82 ' into 'master'" · 1dc76b73
  Pieter Donker authored 1 year ago
  1dc76b73
- RTSD-82 : add indent fix from vsg · 848a1d38
  Pieter Donker authored 1 year ago
  
  848a1d38
Jun 14, 2023
- RTSD-93 , master with all style fixes · de83af40
  Pieter Donker authored 1 year ago
  
  de83af40
May 11, 2023
- Define ddr_gigabytes as integer to be able to represent both > 1GB (HW) and < 1GB (sim) sizes. · aac5f892
  Eric Kooistra authored 2 years ago
  
  aac5f892
Dec 21, 2022
- L2SDP-880 , backup changes · aef102a0
  Pieter Donker authored 2 years ago
  
  aef102a0
Nov 22, 2022
- added unb2c_test_ddr_16G revision · e4f47739
  Reinier van der Walle authored 2 years ago
  
  e4f47739
Nov 15, 2022
- corrected compile_ip.tcl files · 7091023b
  Reinier van der Walle authored 2 years ago
  
  7091023b
Nov 14, 2022
- added 72b ddr4 16G IP + example design · b696ce0e
  Reinier van der Walle authored 2 years ago
  
  b696ce0e
May 04, 2022
- Renamed c_tech_arria10 into c_tech_arria10_proto to more easily find it with e.g. grep. · f26c2268
  Eric Kooistra authored 3 years ago
  
  f26c2268
Jan 19, 2022
- Added missing c_tech_arria10_e2sg => g_ddr4; for unb2c. · cc6e4a47
  Eric Kooistra authored 3 years ago
  
  cc6e4a47
Mar 30, 2021
- unb2c fw update · 0332415e
  Kenneth Hiemstra authored 4 years ago
  
  0332415e
Mar 24, 2021
- modelsim IP models · 6887b788
  Kenneth Hiemstra authored 4 years ago
  
  6887b788
Aug 14, 2020
- Added the IP variant ip_arria10_e1sg_ddr4_16g_1600. · 113074ba
  Reinier van der Walle authored 4 years ago
  
  113074ba
Jul 20, 2020
- Added c_tech_ddr4_8g_1600m_64 · 0577b935
  Reinier van der Walle authored 4 years ago
  
  0577b935
Feb 07, 2020
- New skelton design lofar2_unb2b_adc for ADC testing in the lab · 9cecac99
  Jonathan Hargreaves authored 5 years ago
  9cecac99
Jan 17, 2020
- New IP version e2sg for unb2c using Arria 10AX115U3F45E2SG · f5e8c817
  Jonathan Hargreaves authored 5 years ago
  
  f5e8c817
Dec 03, 2019
- New IP for jesd204b interface; Unb2c test revisions; Add loopback parameter to 10GbE IP · 32fc5d38
  Jonathan Hargreaves authored 5 years ago
  
  32fc5d38
Nov 26, 2019
- changed HDL_BUILD_DIR to RADIOHDL_BUILD_DIR · 7f745007
  Pieter Donker authored 5 years ago
  
  7f745007
Oct 24, 2019
- changed missed library names from 170 to 180 · 963a0fff
  Pieter Donker authored 5 years ago
  
  963a0fff
Oct 21, 2019
- changes mostly in cfg and tcl files for running commandline tools · 9bcacf7a
  Pieter Donker authored 5 years ago
  
  9bcacf7a
Oct 09, 2019
- changes in config files · 81cffcb7
  Pieter Donker authored 5 years ago
  
  81cffcb7
Oct 02, 2019
- changed quartus version from 170 to 180 · 3f602842
  Pieter Donker authored 5 years ago
  
  3f602842
Aug 22, 2019
- backup last changes, build for unb2b not working · b0c776a4
  Pieter Donker authored 5 years ago
  
  b0c776a4
Jul 02, 2018
- added variations for arria10_e1sg and arria10_e3sge3 · f0d129e7
  Reinier van der Walle authored 6 years ago
  
  f0d129e7
Jun 01, 2018
- added instance for arria10_e1sg · 6b909989
  Reinier van der Walle authored 6 years ago
  
  6b909989
Dec 14, 2017
- Added dbg_g_tech_ddr. · ded52197
  Eric Kooistra authored 7 years ago
  
  ded52197
- Added func_tech_ddr_sim_size() to derive (smaller) required DDR size for... · ca735189
  Eric Kooistra authored 7 years ago
  ca735189
- Added debug signals for view in Wave window. · 88f1cb7b
  Eric Kooistra authored 7 years ago
  
  88f1cb7b
Dec 08, 2017
- Imporved g_sim_model description comment. · c8ebfe11
  Eric Kooistra authored 7 years ago
  
  c8ebfe11
Jul 25, 2017
- edited hdllib.cfg and the vhd files of several technology libraries to · dccde9ef
  Reinier van der Walle authored 7 years ago
  dccde9ef
Jun 13, 2017
- Fixed DDR simulation model. · a2f529f6
  Eric Kooistra authored 7 years ago
  
  a2f529f6
- Corrected sim_ddr model, tb_io_ddr now passes with g_sim_model = true. · 57034f10
  Eric Kooistra authored 7 years ago
  
  57034f10
Feb 15, 2017
- Modify technology wrappers to include unb2b FPGA Arria 10 version e1sg · e50aab24
  Jonathan Hargreaves authored 8 years ago
  
  e50aab24
May 17, 2016
- hdl_lib_technology = ip_arria10_e3sge3 · 30568303
  Eric Kooistra authored 9 years ago
  
  30568303
May 12, 2016
- Added regression_test_vhdl, but without tb. · 7f482f03
  Eric Kooistra authored 9 years ago
  
  7f482f03
May 11, 2016
- Added missing library declaration for ip_arria10_e3sge3_ddr4_8g_2400_altera_emif_151 · 691fe3ed
  Eric Kooistra authored 9 years ago
  
  691fe3ed
Apr 28, 2016
- Use hdl_lib_uses_ip for the multiple choice IP. · 80100686
  Eric Kooistra authored 9 years ago
  
  80100686
Apr 19, 2016
- Added [section headers]. · b232c8c7
  Eric Kooistra authored 9 years ago
  
  b232c8c7