changed HDL_BUILD_DIR to RADIOHDL_BUILD_DIR

boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg

@@ -7,7 +7,7 @@ hdl_lib_technology = ip_stratixiv
 synth_files =
     # Commented unb1_bn_capture.vhd and SOPC because only the node is reused.
     # The SOPC causes a simulation error if it not there, because it is instantiated as an entity
-    #$HDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.vhd
+    #$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.vhd
     src/vhdl/unb1_bn_capture_pkg.vhd
     src/vhdl/unb1_bn_capture_input.vhd
     src/vhdl/node_unb1_bn_capture.vhd
@@ -41,7 +41,7 @@ quartus_qsf_files =
 quartus_tcl_files =
     quartus/unb1_bn_capture_pins.tcl
     
-quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.qip
+quartus_qip_files = $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.qip
 
 quartus_sdc_files =
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc

boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg

@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.vhd
     src/vhdl/node_unb1_bn_terminal_bg.vhd
     src/vhdl/unb1_bn_terminal_bg.vhd
     
@@ -31,7 +31,7 @@ quartus_qsf_files =
 quartus_tcl_files =
     quartus/unb1_bn_terminal_bg_pins.tcl
     
-quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.qip
+quartus_qip_files = $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.qip
 
 quartus_sdc_files =
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc

boards/uniboard1/designs/unb1_ddr3/hdllib.cfg

@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
 hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
 
 synth_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.vhd
     src/vhdl/node_unb1_ddr3.vhd
     src/vhdl/mmm_unb1_ddr3.vhd
     src/vhdl/unb1_ddr3.vhd
@@ -31,7 +31,7 @@ quartus_qsf_files =
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.qip
 
 quartus_tcl_files =
     quartus/unb1_ddr3_pins.tcl

boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg

@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
 hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
 
 synth_files =   
-    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.vhd
     ../../src/vhdl/node_unb1_ddr3_reorder.vhd
     ../../src/vhdl/mmm_unb1_ddr3_reorder.vhd
     ../../src/vhdl/unb1_ddr3_reorder.vhd
@@ -42,7 +42,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
     $RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.qip
     
 

boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg

@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
 hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
 
 synth_files =   
-    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.vhd
     ../../src/vhdl/node_unb1_ddr3_reorder.vhd
     ../../src/vhdl/mmm_unb1_ddr3_reorder.vhd
     ../../src/vhdl/unb1_ddr3_reorder.vhd
@@ -42,7 +42,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
     $RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.qip
     
 

boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg

@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
 hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
 
 synth_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd
     src/vhdl/mmm_unb1_ddr3_transpose.vhd
     src/vhdl/unb1_ddr3_transpose.vhd
     
@@ -38,8 +38,8 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
-    $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
+    $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC
 

boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg

@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =   
-    $HDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.vhd
     src/vhdl/mmm_unb1_fn_terminal_db.vhd
     src/vhdl/unb1_fn_terminal_db.vhd
     
@@ -30,7 +30,7 @@ quartus_tcl_files =
     quartus/unb1_fn_terminal_db_pins.tcl
     
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC

boards/uniboard1/designs/unb1_heater/hdllib.cfg

@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_heater/qsys_unb1_heater/synthesis/qsys_unb1_heater.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_heater/qsys_unb1_heater/synthesis/qsys_unb1_heater.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS

boards/uniboard1/designs/unb1_minimal/doc/sopc-to-qsys.txt

@@ -37,7 +37,7 @@ run: rm -rf ~/svn/UniBoard_FP7/RadioHDL/trunk/build/*
         ../../quartus/qsys_unb1_minimal.qsys .
 
     quartus_qip_files =
-        $HDL_BUILD_DIR/quartus/unb1_minimal/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
+        $RADIOHDL_BUILD_DIR/quartus/unb1_minimal/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
 
 11. For future compilations the file qsys_unb1_minimal.qsys
     (after SOPC->QSYS it is this file: ~/RadioHDL/trunk/build/quartus/unb1_minimal/sopc_unb1_minimal.qsys)

boards/uniboard1/designs/unb1_minimal/hdllib.cfg

@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.vhd
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.vhd
     src/vhdl/qsys_unb1_minimal_pkg.vhd
     src/vhdl/mmm_unb1_minimal.vhd
     src/vhdl/unb1_minimal.vhd

boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg

@@ -32,7 +32,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_mm_arbiter/qsys_unb1_minimal_mm_arbiter/synthesis/qsys_unb1_minimal_mm_arbiter.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_mm_arbiter/qsys_unb1_minimal_mm_arbiter/synthesis/qsys_unb1_minimal_mm_arbiter.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS

boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg

@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
 

boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg

@@ -34,7 +34,7 @@ quartus_tcl_files =
 quartus_vhdl_files =
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal/synthesis/qsys_wo_pll_unb1_minimal.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal/synthesis/qsys_wo_pll_unb1_minimal.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS
 

boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg

@@ -32,7 +32,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.qip
 
 nios2_app_userflags = -DCOMPILE_FOR_SOPC
 

boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml

@@ -9,54 +9,52 @@ fpga_description: |
         "unb1_minimal system for sopc"
 
 peripherals:
-  - peripheral_name: rom_system_info
+  - peripheral_name: unb1_board/rom_system
     slave_port_names:
         - rom_system_info
-    parameters:
-      - { name: lock_base_address,  value: 0x1000 }    
+    lock_base_address: 0x1000    
     
-  - peripheral_name: reg_system_info
+  - peripheral_name: unb1_board/system
     slave_port_names:
         - pio_system_info
-    parameters:
-      - { name: lock_base_address, value: 0x0 }    
+    lock_base_address: 0x0    
 
-  - peripheral_name: ctrl_unb1_board
+  - peripheral_name: unb1_board/ctrl_unb1_board
     slave_port_names:
         - pio_wdi
 
-  - peripheral_name: unb1_board_wdi_reg
+  - peripheral_name: unb1_board/unb1_board_wdi_reg
     slave_port_names:
         - reg_wdi
   
-  - peripheral_name: eth1g
+  - peripheral_name: eth/eth1g
     slave_port_names:
         - avs_eth_0_mms_tse
         - avs_eth_0_mms_reg
         - avs_eth_0_mms_ram
     
-  - peripheral_name: ppsh
+  - peripheral_name: ppsh/ppsh
     slave_port_names:
         - pio_pps
 
-  - peripheral_name: epcs_reg
+  - peripheral_name: epcs/epcs_reg
     slave_port_names:
         - reg_epcs
         - reg_mmdp_ctrl
         - reg_mmdp_data
         - reg_dpmm_ctrl
         - reg_dpmm_data
-    parameters:
+    parameter_overrides:
       - { name : g_sim_flash_model, value: FALSE }
 
-  - peripheral_name: remu_reg
+  - peripheral_name: remu/remu_reg
     slave_port_names:
         - reg_remu
 
-  - peripheral_name: unb1_board_sens_reg
+  - peripheral_name: unb1_board/unb1_board_sens_reg
     slave_port_names:
         - reg_unb_sens
-    parameters:
+    parameter_overrides:
       - { name : g_sim,       value: FALSE }
       - { name : g_clk_freq,  value: 125E6 }
       - { name : g_temp_high, value: 85 }

boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg

@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.v
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.v
     src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
     src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
     src/vhdl/unb1_terminal_bg_mesh_db.vhd
@@ -33,7 +33,7 @@ quartus_tcl_files =
     quartus/unb1_terminal_bg_mesh_db_pins.tcl
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.qip
 
 quartus_sdc_files =
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc

boards/uniboard1/designs/unb1_test/doc/README

@@ -121,7 +121,7 @@ The 2nd tcl file can be created with Quartus. Here are the steps:
 - generate the IP's by running: $RADIOHDL_WORK/libraries/technology/ip_stratixiv/generate-all-ip.sh
 - Start synthesis in the Quartus GUI. Only the Analysis step!!
 - Then in Quartus click: Tools/TclScripts. 
-  Open the Tcl file: $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0_pin_assignments.tcl
+  Open the Tcl file: $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0_pin_assignments.tcl
   Click Run.
 - Then Continue synthesis with Fitter, or restart with Analysis.
 - Copy the generated build/unb1_test_ddr_MB_I_II.qsf file to ./designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_MB_I_II_pins_constraints.tcl

boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg

@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS

boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg

@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE_tx_only/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE_tx_only/qsys_unb1_test/synthesis/qsys_unb1_test.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS

boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg

@@ -35,7 +35,7 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $HDL_BUILD_DIR/unb1/quartus/unb1_test_1GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+    $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_1GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
 
 
 nios2_app_userflags = -DCOMPILE_FOR_QSYS