Commits · e4f477395c3e70c7d69eb6ecfb76e0889b9b2571 · RTSD / HDL · GitLab

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May 04, 2022
- Renamed c_tech_arria10 into c_tech_arria10_proto to more easily find it with e.g. grep. · f26c2268
  Eric Kooistra authored 3 years ago
  
  f26c2268
Feb 07, 2020
- New skelton design lofar2_unb2b_adc for ADC testing in the lab · 9cecac99
  Jonathan Hargreaves authored 5 years ago
  9cecac99
Jan 17, 2020
- New IP version e2sg for unb2c using Arria 10AX115U3F45E2SG · f5e8c817
  Jonathan Hargreaves authored 5 years ago
  
  f5e8c817
Jun 01, 2018
- added instance for arria10_e1sg · 6b909989
  Reinier van der Walle authored 7 years ago
  
  6b909989
Dec 08, 2017
- Imporved g_sim_model description comment. · c8ebfe11
  Eric Kooistra authored 7 years ago
  
  c8ebfe11
Jan 29, 2016
- update technology wrapper to include device e3sge3 for unb2a · 16efe183
  Jonathan Hargreaves authored 9 years ago
  
  16efe183
Jun 24, 2015
- -Removed unused signals and constants. · 588a8417
  Daniel van der Schuur authored 9 years ago
  
  588a8417
- -Changed name of generate and instance name to match entity name to ease wave · d2af806a
  Daniel van der Schuur authored 9 years ago
  d2af806a
Jun 12, 2015
- Moved DDR sim model to sim_ddr.vhd. · 201f8808
  Eric Kooistra authored 9 years ago
  
  201f8808
May 06, 2015
- -Added fast behavioural model to tech_ddr.vhd; · cb21fc96
  Daniel van der Schuur authored 10 years ago
  cb21fc96
Apr 08, 2015
- Removed internal DDR memory model (now needs to be instantiated in tb). Use... · 8e1a6162
  Eric Kooistra authored 10 years ago
  8e1a6162
- Removed g_use_ddr_memory_model so the DDR memory model code is not seen/needed... · d51f8638
  Eric Kooistra authored 10 years ago
  d51f8638
- Rename ctlr_ref_clk into ref_clk to have simpler and more clear name. · f1cda4e0
  Eric Kooistra authored 10 years ago
  
  f1cda4e0
Mar 25, 2015
- Renamed g_sim into g_use_ddr_memory_model. · 80ba2261
  Eric Kooistra authored 10 years ago
  
  80ba2261
Mar 11, 2015
- splitted the terminationcontrol lines from the record types... · ed82dce7
  Kenneth Hiemstra authored 10 years ago
  ed82dce7
Feb 20, 2015
- Added g_sim because memory model should not be included in the synthesis · b02115b8
  Zanting authored 10 years ago
  
  b02115b8
Jan 20, 2015
- Added ip_arria10 DDR4 IP for 4Gbyte, 1600 MTps. · 0c910766
  Eric Kooistra authored 10 years ago
  
  0c910766
Jan 08, 2015
- Added g_sim, when TRUE then use internal DDR memory model in tech_ddr... · e8956d9d
  Eric Kooistra authored 10 years ago
  e8956d9d
- Pass on local_init_done from IP via ctlr_miso.done instead of via separate signal ctlr_init_done. · 37b92e7f
  Eric Kooistra authored 10 years ago
  
  37b92e7f
- Clarified ctlr_init_done. · c576df23
  Eric Kooistra authored 10 years ago
  
  c576df23
- Define t_mem_ctlr_mosi/miso in common_mem_pkg, to use that instead of the... · b559785d
  Eric Kooistra authored 10 years ago
  b559785d
Jan 05, 2015
- Rename ctrl into ctlr. · d61c490e
  Eric Kooistra authored 10 years ago
  
  d61c490e
Dec 19, 2014
- Use ddr that supports both ddr3 or ddr4 at this level. · f46f0d8b
  Eric Kooistra authored 10 years ago
  
  f46f0d8b
Dec 18, 2014
- Moved ddr3/ VHDL files to ddr/. · 6d479748
  Eric Kooistra authored 10 years ago
  
  6d479748
- Rename g_ddr into g_tech_ddr · bb69952f
  Eric Kooistra authored 10 years ago
  
  bb69952f
- Gather all DDR parameters in one t_c_tech_ddr record · 3c8fc0e5
  Eric Kooistra authored 10 years ago
  
  3c8fc0e5
Dec 17, 2014
- Added DDR3 IP technology wrapper for straticiv using UniPhy. · 880633c0
  Eric Kooistra authored 10 years ago
  
  880633c0