window navigation in simulation.

-Enabled this model in tb_apertif_unb1_fn_beamformer_tp_bg.

Removed internal DDR memory model (now needs to be instantiated in tb). Use dedicated records for DDR3 and DDR4 phy interfaces, instead of the combined record.

Removed g_use_ddr_memory_model so the DDR memory model code is not seen/needed by synthesis. Instead only support DDR memory model instantiation in test bench.

splitted the terminationcontrol lines from the record types 't_tech_ddr_phy_in' and 't_tech_ddr_phy_ou'

Added g_sim, when TRUE then use internal DDR memory model in tech_ddr component. When FALSE use DDR memory model in test bench.

Define t_mem_ctlr_mosi/miso in common_mem_pkg, to use that instead of the records defined in tech_ddr_pkg. Also remove t_tech_ddr_addr record because it is not needed.