Commits · aac5f8926b3d578522bc581a21276f735c5b1c76 · RTSD / HDL · GitLab

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May 11, 2023
- Define ddr_gigabytes as integer to be able to represent both > 1GB (HW) and < 1GB (sim) sizes. · aac5f892
  Eric Kooistra authored May 11, 2023
  
  aac5f892
Mar 21, 2023
- Add and verify ctlr_nof_bytes_per_word field in reg_io_ddr. · c37576fd
  Eric Kooistra authored Mar 21, 2023
  
  c37576fd
- Add and verify ddr_gigabytes field in reg_io_ddr. · 71e29da7
  Eric Kooistra authored Mar 21, 2023
  
  71e29da7
Mar 20, 2023
- Add c_tech_ddr4_16g_1600m_64, c_tech_ddr4_16g_1600m_72_64 options. · 590e7fd3
  Eric Kooistra authored Mar 20, 2023
  
  590e7fd3
Jan 19, 2022
- Fix simulating DDR4 for unb2c, except for fverifying the dbg_rd_data. · 5174b894
  Eric Kooistra authored Jan 19, 2022
  
  5174b894
- Work around for verifying DDR4 on unb2c. · ae27c70e
  Eric Kooistra authored Jan 19, 2022
  
  ae27c70e
Jul 31, 2018
- fixed the FIXME in io_ddr testbench · f9e6bc4b
  Reinier van der Walle authored Jul 31, 2018
  
  f9e6bc4b
Jun 13, 2017
- Fixed DDR simulation model. · a2f529f6
  Eric Kooistra authored Jun 13, 2017
  
  a2f529f6
Jun 30, 2015
- Removed clock period generics. Corrected c_ctlr_ref_clk_period = 25 MHz for DDR4. · 43931c4b
  Eric Kooistra authored Jun 30, 2015
  
  43931c4b
Jun 26, 2015
- Derive g_rd_fifo_af_margin internally in io_ddr.vhd based on g_tech_ddr.name=DDR3 or DDR4. · 12fd53ea
  Eric Kooistra authored Jun 26, 2015
  
  12fd53ea
Jun 25, 2015
- Used g_cross_domain_delay_len=c_meta_delay_len fixed instead of via generic. · 298065ab
  Eric Kooistra authored Jun 25, 2015
  
  298065ab
Jun 12, 2015
- Added g_sim_model. · 33e83b5a
  Eric Kooistra authored Jun 12, 2015
  
  33e83b5a
Apr 08, 2015
- Removed internal DDR memory model (now needs to be instantiated in tb). Use... · 17ede428
  Eric Kooistra authored Apr 8, 2015
  17ede428
- Removed g_use_ddr_memory_model so the DDR memory model code is not seen/needed... · d51f8638
  Eric Kooistra authored Apr 8, 2015
  d51f8638
Mar 30, 2015
- Added register map in TB · fc4e910c
  Pepping authored Mar 30, 2015
  
  fc4e910c
Mar 25, 2015
- Renamed g_sim into g_use_ddr_memory_model. · 24cd1054
  Eric Kooistra authored Mar 25, 2015
  
  24cd1054
- Corrected g_sim=>TRUE when external memory model is used. · 6a83e240
  Eric Kooistra authored Mar 25, 2015
  
  6a83e240
Jan 23, 2015
- Use g_dp_factor>1 to verify c_rd_fifo_af_margin. · 28b8f1aa
  Eric Kooistra authored Jan 23, 2015
  
  28b8f1aa
- Added g_rd_fifo_depth. · 6ed6463b
  Eric Kooistra authored Jan 23, 2015
  
  6ed6463b
- Improved check on snk_diag_res by placing it after the read FIFO has been read... · 9102d014
  Eric Kooistra authored Jan 23, 2015
  9102d014
Jan 20, 2015
- Improved stimuli using generics and functions to define the write and read block accesses. · b3de752e
  Eric Kooistra authored Jan 20, 2015
  
  b3de752e
Jan 14, 2015
- Define g_tech_ddr as generic. · 5538bc02
  Eric Kooistra authored Jan 14, 2015
  
  5538bc02
Jan 08, 2015
- Added g_sim, when TRUE then use internal DDR memory model in tech_ddr... · e8956d9d
  Eric Kooistra authored Jan 8, 2015
  e8956d9d
- Init dvr_start_address=0 and dvr_nof_data=0. to avoid 'X' after power up. · 22d96617
  Eric Kooistra authored Jan 8, 2015
  
  22d96617
- Wire dvr_done via new dvr_miso.done field instead of via the dvr_miso.waitrequest_n field. · 471d01b1
  Eric Kooistra authored Jan 8, 2015
  
  471d01b1
- Connect dvr_wr_flush_en via dvr_mosi.flush. · 5e468fd4
  Eric Kooistra authored Jan 8, 2015
  
  5e468fd4
- Map original dvr interface signals to dvr_mosi/miso of the record type t_mem_ctlr_mosi/miso. · de3b07b2
  Eric Kooistra authored Jan 8, 2015
  
  de3b07b2
- Check UNSIGNED(wr_fifo_usedw) < c_dp_factor, because a mixed width FIFO cannot... · cb55bd71
  Eric Kooistra authored Jan 8, 2015
  cb55bd71
Jan 07, 2015
- Replaced dvr_end_address by dvr_nof_data. · f77d17f5
  Eric Kooistra authored Jan 7, 2015
  
  f77d17f5
Jan 06, 2015
- Rename dvr_start_addr into dvr_start_address. · aa967f59
  Eric Kooistra authored Jan 6, 2015
  
  aa967f59
- Use ctlr slv address instead of record address. · f9b1a01f
  Eric Kooistra authored Jan 6, 2015
  
  f9b1a01f
- Define g_dp_data_w as generic to be able to select mixed width or equal width FIFO. · d1e0547b
  Eric Kooistra authored Jan 6, 2015
  
  d1e0547b
Jan 05, 2015
- Removed ctrl_rdy. Instead better use dvr_done to monitor the DDR state via a MM register if needed. · ac1d2c4c
  Eric Kooistra authored Jan 5, 2015
  
  ac1d2c4c
- Removed ctlr_init_done. Now report ctlr_init_done via dvr_done. · a7a0c44b
  Eric Kooistra authored Jan 5, 2015
  
  a7a0c44b
- Added io_ddr_cross_domain.vhd to handle dvr_clk and ctlr_clk domains in case... · f52fc96d
  Eric Kooistra authored Jan 5, 2015
  f52fc96d
- Use g_technology generic.diff · 6f9ec37a
  Eric Kooistra authored Jan 5, 2015
  
  6f9ec37a
Dec 23, 2014
- Support g_wr_flush_mode = VAL, SOP, SYN. · 2b15c467
  Eric Kooistra authored Dec 23, 2014
  
  2b15c467
- Added dvr_wr_fifo_usedw output for monitoring purposes, eg. used for verification in tb_io_ddr.vhd. · 0769c3b1
  Eric Kooistra authored Dec 23, 2014
  
  0769c3b1
- Redefined write flush modes. Now the flush is still under control by... · 122facc2
  Eric Kooistra authored Dec 23, 2014
  122facc2
- Improved verification by using multiple fragmented wr and rd accesses. · 61bd9e67
  Eric Kooistra authored Dec 23, 2014
  
  61bd9e67