Commits · 1dc76b73ec19f61868ba16fcc366fcb9dc55008a · RTSD / HDL

Aug 16, 2023
- Revert "Merge branch 'RTSD-82 ' into 'master'" · 1dc76b73
  Pieter Donker authored 1 year ago
  
  This reverts commit ef19a04f, reversing changes made to 4a55fb28.
  1dc76b73
- RTSD-82 : add indent fix from vsg · 848a1d38
  Pieter Donker authored 1 year ago
  
  848a1d38
Jun 15, 2023
- RTSD-93 , review comment 1 · 9a9fba3d
  Pieter Donker authored 1 year ago
  
  9a9fba3d
Jun 14, 2023
- RTSD-93 , master with all style fixes · de83af40
  Pieter Donker authored 1 year ago
  
  de83af40
May 11, 2023
- Define ddr_gigabytes as integer to be able to represent both > 1GB (HW) and < 1GB (sim) sizes. · aac5f892
  Eric Kooistra authored 1 year ago
  
  aac5f892
May 09, 2023
- processed review comments · 8de6da56
  Reinier van der Walle authored 1 year ago
  
  8de6da56
May 08, 2023
- cleanup · 91d4cc9a
  Reinier van der Walle authored 1 year ago
  
  91d4cc9a
May 02, 2023
- typo fix · aaec1ead
  Reinier van der Walle authored 1 year ago
  
  aaec1ead
Apr 18, 2023
- removed constant usage for Vivado IP packager · 3db7f083
  Reinier van der Walle authored 1 year ago
  
  3db7f083
- corrected syntax · 3ed294cf
  Reinier van der Walle authored 1 year ago
  
  3ed294cf
- updated tech lib to support ultrascale ram IPs · 56102f69
  Reinier van der Walle authored 1 year ago
  
  56102f69
- added ultrascale fifo IPs · d6076466
  Reinier van der Walle authored 1 year ago
  
  d6076466
Apr 17, 2023
- added XMP templates for ip_ultrascale_ram · c5ff152a
  Reinier van der Walle authored 1 year ago
  
  c5ff152a
Apr 11, 2023
- initial commit of ported Block RAM · 32c433b0
  Reinier van der Walle authored 1 year ago
  
  32c433b0
Jan 27, 2023
- Revert "corrected compile_ip.tcl" · be60ae75
  Reinier van der Walle authored 2 years ago
  
  This reverts commit c0e6e66d
  be60ae75
Jan 17, 2023
- corrected compile_ip.tcl · c0e6e66d
  Reinier van der Walle authored 2 years ago
  
  c0e6e66d
- processed review comments · bcba7953
  Reinier van der Walle authored 2 years ago
  
  bcba7953
Jan 13, 2023
- Removed modelsim error by excluding the remote_update and asmi_parallel · 3eb322c4
  Reinier van der Walle authored 2 years ago
  
  in VHDL
  3eb322c4
Dec 21, 2022
- L2SDP-880 , backup changes · aef102a0
  Pieter Donker authored 2 years ago
  
  aef102a0
Dec 20, 2022
- Default support jumbo frames. · 17c00f82
  Eric Kooistra authored 2 years ago
  
  17c00f82
Dec 19, 2022
- corrected tb and added PCS registers · 907f9d0d
  Reinier van der Walle authored 2 years ago
  
  907f9d0d
- corrected address width · bcf1b2e3
  Reinier van der Walle authored 2 years ago
  
  bcf1b2e3
- corrected address of TSE IP · 0d50063f
  Reinier van der Walle authored 2 years ago
  
  0d50063f
Nov 29, 2022
- Expected TSE version depends on FPGA / Uniboard1,2 type. · d03ec2e7
  Eric Kooistra authored 2 years ago
  
  d03ec2e7
Nov 22, 2022
- Add tech_tse_with_setup.vhd and test bench. · b57c3e7a
  Eric Kooistra authored 2 years ago
  
  b57c3e7a
- Add signals to view data word in Wave window. · b3f01d9c
  Eric Kooistra authored 2 years ago
  
  b3f01d9c
- added unb2c_test_ddr_16G revision · e4f47739
  Reinier van der Walle authored 2 years ago
  
  e4f47739
Nov 15, 2022
- corrected compile_ip.tcl files · 7091023b
  Reinier van der Walle authored 2 years ago
  
  7091023b
Nov 14, 2022
- corrected IP revision hashes used in tcl scripts · a2cb4855
  Reinier van der Walle authored 2 years ago
  
  a2cb4855
- added 72b ddr4 16G IP + example design · b696ce0e
  Reinier van der Walle authored 2 years ago
  
  b696ce0e
Nov 07, 2022
- added 16G ddr4 IP and created example design. · 01fad539
  Reinier van der Walle authored 2 years ago
  
  01fad539
Jul 12, 2022
- corrected PIO_JESD_CTRL description in yaml · 015b58d1
  Reinier van der Walle authored 2 years ago
  
  015b58d1
May 31, 2022
- Added comment. · de677b66
  Eric Kooistra authored 2 years ago
  
  de677b66
- Added missing JESD204B MM register fields. · d2e1f4e6
  Eric Kooistra authored 2 years ago
  
  d2e1f4e6
- Explained that JESD2044 MM registers have 256 bytes, so span_w = 6 would be... · 43d0276a
  Eric Kooistra authored 2 years ago
  
  Explained that JESD2044 MM registers have 256 bytes, so span_w = 6 would be enough, but 8 is fine too.
  43d0276a
- Verify jesd204b_rddata. · 314010b7
  Eric Kooistra authored 2 years ago
  
  314010b7
- Use word addresses and add more registers from registermap-jesd-rx.xlsx. · d06d23d4
  Eric Kooistra authored 2 years ago
  
  d06d23d4
- Support jesd_miso rdval. · e3dae31e
  Eric Kooistra authored 2 years ago
  
  e3dae31e
May 30, 2022
- Pass on g_jesd_freq, same for e2sg as for e1sg. · d249b825
  Eric Kooistra authored 2 years ago
  
  d249b825
- Connect missing IN jesd204b_disable_arr. · cedf3887
  Eric Kooistra authored 2 years ago
  
  cedf3887