added ultrascale fifo IPs

libraries/technology/fifo/hdllib.cfg

 hdl_lib_name = tech_fifo
 hdl_library_clause_name = tech_fifo_lib
-hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo ip_arria10_e1sg_fifo ip_arria10_e2sg_fifo
+hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo ip_arria10_e1sg_fifo ip_arria10_e2sg_fifo ip_ultrascale_fifo
 hdl_lib_uses_sim = 
 hdl_lib_technology = 
 hdl_lib_disclose_library_clause_names =
@@ -9,6 +9,7 @@ hdl_lib_disclose_library_clause_names =
     ip_arria10_e3sge3_fifo ip_arria10_e3sge3_fifo_lib
     ip_arria10_e1sg_fifo   ip_arria10_e1sg_fifo_lib
     ip_arria10_e2sg_fifo   ip_arria10_e2sg_fifo_lib
+    ip_ultrascale_fifo     ip_arria10_ultrascale_lib
 
 synth_files =
     tech_fifo_component_pkg.vhd

libraries/technology/fifo/tech_fifo_component_pkg.vhd

@@ -352,5 +352,67 @@ PACKAGE tech_fifo_component_pkg IS
   );
   END COMPONENT;
    
+  -----------------------------------------------------------------------------
+  -- ip_ultrascale
+  -----------------------------------------------------------------------------
+  
+  COMPONENT ip_ultrascale_fifo_sc IS
+  GENERIC (
+    g_dat_w     : NATURAL := 20;
+    g_nof_words : NATURAL := 1024
+  );
+  PORT (
+    aclr    : IN STD_LOGIC ;
+    clock   : IN STD_LOGIC ;
+    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdreq   : IN STD_LOGIC ;
+    wrreq   : IN STD_LOGIC ;
+    empty   : OUT STD_LOGIC ;
+    full    : OUT STD_LOGIC ;
+    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
+    usedw   : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+  END COMPONENT;
+
+  COMPONENT ip_ultrascale_fifo_dc IS
+  GENERIC (
+    g_dat_w     : NATURAL := 20;
+    g_nof_words : NATURAL := 1024
+  );
+  PORT (
+    aclr    : IN STD_LOGIC  := '0';
+    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdclk   : IN STD_LOGIC ;
+    rdreq   : IN STD_LOGIC ;
+    wrclk   : IN STD_LOGIC ;
+    wrreq   : IN STD_LOGIC ;
+    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdempty : OUT STD_LOGIC ;
+    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
+    wrfull  : OUT STD_LOGIC ;
+    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+  END COMPONENT;
+  
+  COMPONENT ip_ultrascale_fifo_dc_mixed_widths IS
+  GENERIC (
+    g_nof_words : NATURAL := 1024;  -- FIFO size in nof wr_dat words
+    g_wrdat_w   : NATURAL := 20;
+    g_rddat_w   : NATURAL := 10
+  );
+  PORT (
+    aclr    : IN STD_LOGIC  := '0';
+    data    : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
+    rdclk   : IN STD_LOGIC ;
+    rdreq   : IN STD_LOGIC ;
+    wrclk   : IN STD_LOGIC ;
+    wrreq   : IN STD_LOGIC ;
+    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
+    rdempty : OUT STD_LOGIC ;
+    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
+    wrfull  : OUT STD_LOGIC ;
+    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+  END COMPONENT;
   
 END tech_fifo_component_pkg;

libraries/technology/fifo/tech_fifo_dc.vhd

@@ -31,6 +31,7 @@ LIBRARY ip_arria10_fifo_lib;
 LIBRARY ip_arria10_e3sge3_fifo_lib;
 LIBRARY ip_arria10_e1sg_fifo_lib;
 LIBRARY ip_arria10_e2sg_fifo_lib;
+LIBRARY ip_ultrascale_fifo_lib;
 
 ENTITY tech_fifo_dc IS
   GENERIC (
@@ -89,4 +90,10 @@ BEGIN
     PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
   END GENERATE;
 
+  gen_ip_ultrascale : IF g_technology=c_tech_ultrascale GENERATE
+    u0 : ip_ultrascale_fifo_dc
+    GENERIC MAP (g_dat_w, g_nof_words)
+    PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+  END GENERATE;
+
 END ARCHITECTURE;

libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd

@@ -31,6 +31,7 @@ LIBRARY ip_arria10_fifo_lib;
 LIBRARY ip_arria10_e3sge3_fifo_lib;
 LIBRARY ip_arria10_e1sg_fifo_lib;
 LIBRARY ip_arria10_e2sg_fifo_lib;
+LIBRARY ip_ultrascale_fifo_lib;
 
 ENTITY tech_fifo_dc_mixed_widths IS
   GENERIC (
@@ -89,4 +90,10 @@ BEGIN
     PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
   END GENERATE;
  
+  gen_ip_ultrascale : IF g_technology=c_tech_ultrascale GENERATE
+    u0 : ip_ultrascale_fifo_dc_mixed_widths
+    GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
+    PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+  END GENERATE;
+
 END ARCHITECTURE;

libraries/technology/fifo/tech_fifo_sc.vhd

@@ -31,6 +31,7 @@ LIBRARY ip_arria10_fifo_lib;
 LIBRARY ip_arria10_e3sge3_fifo_lib;
 LIBRARY ip_arria10_e1sg_fifo_lib;
 LIBRARY ip_arria10_e2sg_fifo_lib;
+LIBRARY ip_ultrascale_fifo_lib;
 
 ENTITY tech_fifo_sc IS
   GENERIC (
@@ -87,4 +88,10 @@ BEGIN
     PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
   END GENERATE;
   
+  gen_ip_ultrascale : IF g_technology=c_tech_ultrascale GENERATE
+    u0 : ip_ultrascale_fifo_sc
+    GENERIC MAP (g_dat_w, g_nof_words)
+    PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
+  END GENERATE;
+
 END ARCHITECTURE;

libraries/technology/ip_ultrascale/fifo/README.txt

+README.txt for $HDL_WORK/libraries/technology/ip_arria10/fifo
+
+Contents:
+
+1) FIFO components
+2) Arria10 IP
+3) Implementation options (LUTs or block RAM)
+4) Synthesis trials
+5) Issues
+
+
+1) FIFO components:
+
+  ip_arria10_fifo_sc              = Single clock FIFO
+  ip_arria10_fifo_dc              = Dual clock FIFO
+  ip_arria10_fifo_dc_mixed_widths = Dual clock FIFO with different read and write data widths (ratio power of 2)
+  
+
+2) Arria10 IP
+
+  The IP was ported from Stratix IV by:
+  
+    . copy original MegaWizard <fifo_name>.vhd file
+    . rename <fifo_name>.vhd into ip_arria10_<fifo_name>.vhd (also replace name inside the file)
+    . commit the fifo/ip_arria10_<fifo_name>.vhd to preserve the MegaWizard original
+    . open in to Quartus 14, set device family to Arria10 and finish automatically convert to Qsys
+    . then generate HDL (select VHDL for both sim and synth) and finish to save it as ip_arria10_<fifo_name>.qsys
+    
+  this yields:
+  
+    ip_arria10_fifo_sc.qsys
+    ip_arria10_fifo_dc.qsys
+    ip_arria10_fifo_dc_mixed_widths.qsys
+  
+  The Arria10 FIFO IP still uses the altera_mf package (so not the altera_lnsim package as with the block RAM). The
+  FIFOs map to the altera_mf components to scfifo, dcfifo and dcfifo_mixed_widths.
+  
+  The IP only needs to be generated with ./generate_ip.sh if it need to be modified, because the ip_arria10_fifo_*.vhd
+  directly instantiates the altera_mf component.
+  
+  The instantiation is copied manually from the ip_arria10_fifo_*/fifo_140/sim/ip_arria10_fifo_*.vhd and 
+  saved in the <fifo_name>.vhd file. So then the MegaWizard vhd file is overwritten, but that is fine because it is 
+  no longer needed, it could easily be derived from the original in $UNB and it is still as a previous verion in SVN.
+   
+
+3) Implementation options (LUTs or block RAM)
+
+  The IP FIFO can be set to use LUTs (MLAB) or block RAM (M20K) via g_use_eab.
+  
+
+4) Synthesis trials
+
+  The quartus/fifo.qpf Quartus project was used to verify that the FIFO IP actually synthesise to the appropriate FPGA resources.
+  Use the Quartus GUI to manually select a top level component for synthesis e.g. by right clicking the entity vhd file
+  in the file tab of the Quartus project navigator window.
+  Then check the resource usage in the synthesis and fitter reports.
+
+
+5) Issues
+
+  No issues.
\ No newline at end of file

libraries/technology/ip_ultrascale/fifo/hdllib.cfg

+hdl_lib_name = ip_ultrascale_fifo
+hdl_library_clause_name = ip_ultrascale_fifo_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_ultrascale
+
+synth_files =
+    ip_ultrascale_fifo_sc.vhd
+    ip_ultrascale_fifo_dc.vhd
+    ip_ultrascale_fifo_dc_mixed_widths.vhd
+    
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+

libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Purpose: Instantiate FIFO IP with generics
+-- Description:
+--   Copied component instantiation from Vivado XPM template
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY technology_lib;
+USE technology_lib.technology_pkg.ALL;
+
+LIBRARY xpm;
+USE xpm.vcomponents.ALL;
+
+ENTITY ip_ultrascale_fifo_dc IS
+  GENERIC (
+    g_dat_w     : NATURAL := 20;
+    g_nof_words : NATURAL := 1024
+  );
+  PORT (
+    aclr    : IN STD_LOGIC  := '0';
+    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdclk   : IN STD_LOGIC ;
+    rdreq   : IN STD_LOGIC ;
+    wrclk   : IN STD_LOGIC ;
+    wrreq   : IN STD_LOGIC ;
+    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdempty : OUT STD_LOGIC ;
+    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
+    wrfull  : OUT STD_LOGIC ;
+    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+END ip_ultrascale_fifo_dc;
+
+
+ARCHITECTURE SYN OF ip_ultrascale_fifo_dc IS
+
+BEGIN
+
+   -- xpm_fifo_async: Asynchronous FIFO
+   -- Xilinx Parameterized Macro, version 2022.1
+
+   xpm_fifo_async_inst : xpm_fifo_async
+   generic map (
+      CASCADE_HEIGHT => 0,        -- DECIMAL
+      CDC_SYNC_STAGES => 3,       -- DECIMAL
+      DOUT_RESET_VALUE => "0",    -- String
+      ECC_MODE => "no_ecc",       -- String
+      FIFO_MEMORY_TYPE => "auto", -- String
+      FIFO_READ_LATENCY => 1,     -- DECIMAL
+      FIFO_WRITE_DEPTH => g_nof_words,   -- DECIMAL
+      FULL_RESET_VALUE => 0,      -- DECIMAL
+      PROG_EMPTY_THRESH => 10,    -- DECIMAL
+      PROG_FULL_THRESH => 10,     -- DECIMAL
+      RD_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words),   -- DECIMAL
+      READ_DATA_WIDTH => g_dat_w,  -- DECIMAL
+      READ_MODE => "std",          -- String
+      RELATED_CLOCKS => 0,         -- DECIMAL
+      SIM_ASSERT_CHK => 0,         -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      USE_ADV_FEATURES => "0404",  -- String
+      WAKEUP_TIME => 0,            -- DECIMAL
+      WRITE_DATA_WIDTH => g_dat_w, -- DECIMAL
+      WR_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words)    -- DECIMAL
+   )
+   port map (
+      almost_empty => OPEN,        -- 1-bit output: Almost Empty : When asserted, this signal indicates that
+                                      -- only one more read can be performed before the FIFO goes to empty.
+
+      almost_full => OPEN,     -- 1-bit output: Almost Full: When asserted, this signal indicates that
+                                      -- only one more write can be performed before the FIFO is full.
+
+      data_valid => OPEN,       -- 1-bit output: Read Data Valid: When asserted, this signal indicates
+                                      -- that valid data is available on the output bus (dout).
+
+      dbiterr => OPEN,             -- 1-bit output: Double Bit Error: Indicates that the ECC decoder
+                                      -- detected a double-bit error and data in the FIFO core is corrupted.
+
+      dout => q,                      -- READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven
+                                      -- when reading the FIFO.
+
+      empty => rdempty,               -- 1-bit output: Empty Flag: When asserted, this signal indicates that
+                                      -- the FIFO is empty. Read requests are ignored when the FIFO is empty,
+                                      -- initiating a read while empty is not destructive to the FIFO.
+
+      full => wrfull,                 -- 1-bit output: Full Flag: When asserted, this signal indicates that the
+                                      -- FIFO is full. Write requests are ignored when the FIFO is full,
+                                      -- initiating a write when the FIFO is full is not destructive to the
+                                      -- contents of the FIFO.
+
+      overflow => OPEN,               -- 1-bit output: Overflow: This signal indicates that a write request
+                                      -- (wren) during the prior clock cycle was rejected, because the FIFO is
+                                      -- full. Overflowing the FIFO is not destructive to the contents of the
+                                      -- FIFO.
+
+      prog_empty => OPEN,             -- 1-bit output: Programmable Empty: This signal is asserted when the
+                                      -- number of words in the FIFO is less than or equal to the programmable
+                                      -- empty threshold value. It is de-asserted when the number of words in
+                                      -- the FIFO exceeds the programmable empty threshold value.
+
+      prog_full => OPEN,              -- 1-bit output: Programmable Full: This signal is asserted when the
+                                      -- number of words in the FIFO is greater than or equal to the
+                                      -- programmable full threshold value. It is de-asserted when the number
+                                      -- of words in the FIFO is less than the programmable full threshold
+                                      -- value.
+
+      rd_data_count => rdusedw,       -- RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates
+                                      -- the number of words read from the FIFO.
+
+      rd_rst_busy => OPEN,            -- 1-bit output: Read Reset Busy: Active-High indicator that the FIFO
+                                      -- read domain is currently in a reset state.
+
+      sbiterr => OPEN,                -- 1-bit output: Single Bit Error: Indicates that the ECC decoder
+                                      -- detected and fixed a single-bit error.
+
+      underflow => OPEN,              -- 1-bit output: Underflow: Indicates that the read request (rd_en)
+                                      -- during the previous clock cycle was rejected because the FIFO is
+                                      -- empty. Under flowing the FIFO is not destructive to the FIFO.
+
+      wr_ack => OPEN,                 -- 1-bit output: Write Acknowledge: This signal indicates that a write
+                                      -- request (wr_en) during the prior clock cycle is succeeded.
+
+      wr_data_count => wrusedw,       -- WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates
+                                      -- the number of words written into the FIFO.
+
+      wr_rst_busy => OPEN,            -- 1-bit output: Write Reset Busy: Active-High indicator that the FIFO
+                                      -- write domain is currently in a reset state.
+
+      din => data,                    -- WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when
+                                      -- writing the FIFO.
+
+      injectdbiterr => '0',           -- 1-bit input: Double Bit Error Injection: Injects a double bit error if
+                                      -- the ECC feature is used on block RAMs or UltraRAM macros.
+
+      injectsbiterr => '0',           -- 1-bit input: Single Bit Error Injection: Injects a single bit error if
+                                      -- the ECC feature is used on block RAMs or UltraRAM macros.
+
+      rd_clk => rdclk,                -- 1-bit input: Read clock: Used for read operation. rd_clk must be a
+                                      -- free running clock.
+
+      rd_en => rdreq,                 -- 1-bit input: Read Enable: If the FIFO is not empty, asserting this
+                                      -- signal causes data (on dout) to be read from the FIFO. Must be held
+                                      -- active-low when rd_rst_busy is active high.
+
+      rst => aclr,                     -- 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be
+                                      -- unstable at the time of applying reset, but reset must be released
+                                      -- only after the clock(s) is/are stable.
+
+      sleep => '0',                   -- 1-bit input: Dynamic power saving: If sleep is High, the memory/fifo
+                                      -- block is in power saving mode.
+
+      wr_clk => wrclk,                -- 1-bit input: Write clock: Used for write operation. wr_clk must be a
+                                      -- free running clock.
+
+      wr_en => wrreq                  -- 1-bit input: Write Enable: If the FIFO is not full, asserting this
+                                      -- signal causes data (on din) to be written to the FIFO. Must be held
+                                      -- active-low when rst or wr_rst_busy is active high.
+
+   );
+
+   -- End of xpm_fifo_async_inst instantiation
+
+END SYN;

libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc_mixed_widths.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Purpose: Instantiate FIFO IP with generics
+-- Description:
+--   Copied component instantiation from Vivado XPM template
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY technology_lib;
+USE technology_lib.technology_pkg.ALL;
+
+LIBRARY xpm;
+USE xpm.vcomponents.ALL;
+
+ENTITY ip_ultrascale_fifo_dc_mixed_widths IS
+  GENERIC (
+    g_nof_words : NATURAL := 1024;  -- FIFO size in nof wr_dat words
+    g_wrdat_w   : NATURAL := 20;
+    g_rddat_w   : NATURAL := 10
+  );
+  PORT (
+    aclr    : IN STD_LOGIC  := '0';
+    data    : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
+    rdclk   : IN STD_LOGIC ;
+    rdreq   : IN STD_LOGIC ;
+    wrclk   : IN STD_LOGIC ;
+    wrreq   : IN STD_LOGIC ;
+    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
+    rdempty : OUT STD_LOGIC ;
+    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
+    wrfull  : OUT STD_LOGIC ;
+    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+END ip_ultrascale_fifo_dc_mixed_widths;
+
+
+ARCHITECTURE SYN OF ip_ultrascale_fifo_dc_mixed_widths IS
+
+    
+BEGIN
+
+
+
+   -- xpm_fifo_async: Asynchronous FIFO
+   -- Xilinx Parameterized Macro, version 2022.1
+
+   xpm_fifo_async_inst : xpm_fifo_async
+   generic map (
+      CASCADE_HEIGHT => 0,        -- DECIMAL
+      CDC_SYNC_STAGES => 3,       -- DECIMAL
+      DOUT_RESET_VALUE => "0",    -- String
+      ECC_MODE => "no_ecc",       -- String
+      FIFO_MEMORY_TYPE => "auto", -- String
+      FIFO_READ_LATENCY => 1,     -- DECIMAL
+      FIFO_WRITE_DEPTH => g_nof_words,   -- DECIMAL
+      FULL_RESET_VALUE => 0,      -- DECIMAL
+      PROG_EMPTY_THRESH => 10,    -- DECIMAL
+      PROG_FULL_THRESH => 10,     -- DECIMAL
+      RD_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w),   -- DECIMAL
+      READ_DATA_WIDTH => g_rddat_w,      -- DECIMAL
+      READ_MODE => "std",         -- String
+      RELATED_CLOCKS => 0,        -- DECIMAL
+      SIM_ASSERT_CHK => 0,        -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      USE_ADV_FEATURES => "0404", -- String
+      WAKEUP_TIME => 0,           -- DECIMAL
+      WRITE_DATA_WIDTH => g_wrdat_w,     -- DECIMAL
+      WR_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words)    -- DECIMAL
+   )
+   port map (
+      almost_empty => OPEN,        -- 1-bit output: Almost Empty : When asserted, this signal indicates that
+                                      -- only one more read can be performed before the FIFO goes to empty.
+
+      almost_full => OPEN,     -- 1-bit output: Almost Full: When asserted, this signal indicates that
+                                      -- only one more write can be performed before the FIFO is full.
+
+      data_valid => OPEN,       -- 1-bit output: Read Data Valid: When asserted, this signal indicates
+                                      -- that valid data is available on the output bus (dout).
+
+      dbiterr => OPEN,             -- 1-bit output: Double Bit Error: Indicates that the ECC decoder
+                                      -- detected a double-bit error and data in the FIFO core is corrupted.
+
+      dout => q,                      -- READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven
+                                      -- when reading the FIFO.
+
+      empty => rdempty,               -- 1-bit output: Empty Flag: When asserted, this signal indicates that
+                                      -- the FIFO is empty. Read requests are ignored when the FIFO is empty,
+                                      -- initiating a read while empty is not destructive to the FIFO.
+
+      full => wrfull,                 -- 1-bit output: Full Flag: When asserted, this signal indicates that the
+                                      -- FIFO is full. Write requests are ignored when the FIFO is full,
+                                      -- initiating a write when the FIFO is full is not destructive to the
+                                      -- contents of the FIFO.
+
+      overflow => OPEN,               -- 1-bit output: Overflow: This signal indicates that a write request
+                                      -- (wren) during the prior clock cycle was rejected, because the FIFO is
+                                      -- full. Overflowing the FIFO is not destructive to the contents of the
+                                      -- FIFO.
+
+      prog_empty => OPEN,             -- 1-bit output: Programmable Empty: This signal is asserted when the
+                                      -- number of words in the FIFO is less than or equal to the programmable
+                                      -- empty threshold value. It is de-asserted when the number of words in
+                                      -- the FIFO exceeds the programmable empty threshold value.
+
+      prog_full => OPEN,              -- 1-bit output: Programmable Full: This signal is asserted when the
+                                      -- number of words in the FIFO is greater than or equal to the
+                                      -- programmable full threshold value. It is de-asserted when the number
+                                      -- of words in the FIFO is less than the programmable full threshold
+                                      -- value.
+
+      rd_data_count => rdusedw,       -- RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates
+                                      -- the number of words read from the FIFO.
+
+      rd_rst_busy => OPEN,            -- 1-bit output: Read Reset Busy: Active-High indicator that the FIFO
+                                      -- read domain is currently in a reset state.
+
+      sbiterr => OPEN,                -- 1-bit output: Single Bit Error: Indicates that the ECC decoder
+                                      -- detected and fixed a single-bit error.
+
+      underflow => OPEN,              -- 1-bit output: Underflow: Indicates that the read request (rd_en)
+                                      -- during the previous clock cycle was rejected because the FIFO is
+                                      -- empty. Under flowing the FIFO is not destructive to the FIFO.
+
+      wr_ack => OPEN,                 -- 1-bit output: Write Acknowledge: This signal indicates that a write
+                                      -- request (wr_en) during the prior clock cycle is succeeded.
+
+      wr_data_count => wrusedw,       -- WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates
+                                      -- the number of words written into the FIFO.
+
+      wr_rst_busy => OPEN,            -- 1-bit output: Write Reset Busy: Active-High indicator that the FIFO
+                                      -- write domain is currently in a reset state.
+
+      din => data,                    -- WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when
+                                      -- writing the FIFO.
+
+      injectdbiterr => '0',           -- 1-bit input: Double Bit Error Injection: Injects a double bit error if
+                                      -- the ECC feature is used on block RAMs or UltraRAM macros.
+
+      injectsbiterr => '0',           -- 1-bit input: Single Bit Error Injection: Injects a single bit error if
+                                      -- the ECC feature is used on block RAMs or UltraRAM macros.
+
+      rd_clk => rdclk,                -- 1-bit input: Read clock: Used for read operation. rd_clk must be a
+                                      -- free running clock.
+
+      rd_en => rdreq,                 -- 1-bit input: Read Enable: If the FIFO is not empty, asserting this
+                                      -- signal causes data (on dout) to be read from the FIFO. Must be held
+                                      -- active-low when rd_rst_busy is active high.
+
+      rst => aclr,                     -- 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be
+                                      -- unstable at the time of applying reset, but reset must be released
+                                      -- only after the clock(s) is/are stable.
+
+      sleep => '0',                   -- 1-bit input: Dynamic power saving: If sleep is High, the memory/fifo
+                                      -- block is in power saving mode.
+
+      wr_clk => wrclk,                -- 1-bit input: Write clock: Used for write operation. wr_clk must be a
+                                      -- free running clock.
+
+      wr_en => wrreq                  -- 1-bit input: Write Enable: If the FIFO is not full, asserting this
+                                      -- signal causes data (on din) to be written to the FIFO. Must be held
+                                      -- active-low when rst or wr_rst_busy is active high.
+
+   );
+
+   -- End of xpm_fifo_async_inst instantiation
+
+
+END SYN;

libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_sc.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Purpose: Instantiate FIFO IP with generics
+-- Description:
+--   Copied component instantiation from Vivado XPM template
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY technology_lib;
+USE technology_lib.technology_pkg.ALL;
+
+LIBRARY xpm;
+USE xpm.vcomponents.ALL;
+
+ENTITY ip_ultrascale_fifo_sc IS
+  GENERIC (
+    g_dat_w     : NATURAL := 20;
+    g_nof_words : NATURAL := 1024
+  );
+  PORT (
+    aclr    : IN STD_LOGIC ;
+    clock   : IN STD_LOGIC ;
+    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdreq   : IN STD_LOGIC ;
+    wrreq   : IN STD_LOGIC ;
+    empty   : OUT STD_LOGIC ;
+    full    : OUT STD_LOGIC ;
+    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
+    usedw   : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+END ip_ultrascale_fifo_sc;
+
+
+ARCHITECTURE SYN OF ip_ultrascale_fifo_sc IS
+
+BEGIN
+   -- xpm_fifo_sync: Synchronous FIFO
+   -- Xilinx Parameterized Macro, version 2022.1
+
+   xpm_fifo_sync_inst : xpm_fifo_sync
+   generic map (
+      CASCADE_HEIGHT => 0,        -- DECIMAL
+      DOUT_RESET_VALUE => "0",    -- String
+      ECC_MODE => "no_ecc",       -- String
+      FIFO_MEMORY_TYPE => "auto", -- String
+      FIFO_READ_LATENCY => 1,     -- DECIMAL
+      FIFO_WRITE_DEPTH => g_nof_words,   -- DECIMAL
+      FULL_RESET_VALUE => 0,      -- DECIMAL
+      PROG_EMPTY_THRESH => 10,    -- DECIMAL
+      PROG_FULL_THRESH => 10,     -- DECIMAL
+      RD_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words),   -- DECIMAL
+      READ_DATA_WIDTH => g_dat_w,  -- DECIMAL
+      READ_MODE => "std",         -- String
+      SIM_ASSERT_CHK => 0,        -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      USE_ADV_FEATURES => "0404",  -- String
+      WAKEUP_TIME => 0,           -- DECIMAL
+      WRITE_DATA_WIDTH => g_dat_w, -- DECIMAL
+      WR_DATA_COUNT_WIDTH => tech_ceil_log2(g_nof_words)    -- DECIMAL
+
+   )
+   port map (
+      almost_empty => OPEN,           -- 1-bit output: Almost Empty : When asserted, this signal indicates that
+                                      -- only one more read can be performed before the FIFO goes to empty.
+
+      almost_full => OPEN,            -- 1-bit output: Almost Full: When asserted, this signal indicates that
+                                      -- only one more write can be performed before the FIFO is full.
+
+      data_valid => OPEN,             -- 1-bit output: Read Data Valid: When asserted, this signal indicates
+                                      -- that valid data is available on the output bus (dout).
+
+      dbiterr => OPEN,                -- 1-bit output: Double Bit Error: Indicates that the ECC decoder
+                                      -- detected a double-bit error and data in the FIFO core is corrupted.
+
+      dout => q,                      -- READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven
+                                      -- when reading the FIFO.
+
+      empty => empty,                 -- 1-bit output: Empty Flag: When asserted, this signal indicates that
+                                      -- the FIFO is empty. Read requests are ignored when the FIFO is empty,
+                                      -- initiating a read while empty is not destructive to the FIFO.
+
+      full => full,                   -- 1-bit output: Full Flag: When asserted, this signal indicates that the
+                                      -- FIFO is full. Write requests are ignored when the FIFO is full,
+                                      -- initiating a write when the FIFO is full is not destructive to the
+                                      -- contents of the FIFO.
+
+      overflow => OPEN,               -- 1-bit output: Overflow: This signal indicates that a write request
+                                      -- (wren) during the prior clock cycle was rejected, because the FIFO is
+                                      -- full. Overflowing the FIFO is not destructive to the contents of the
+                                      -- FIFO.
+
+      prog_empty => OPEN,             -- 1-bit output: Programmable Empty: This signal is asserted when the
+                                      -- number of words in the FIFO is less than or equal to the programmable
+                                      -- empty threshold value. It is de-asserted when the number of words in
+                                      -- the FIFO exceeds the programmable empty threshold value.
+
+      prog_full => OPEN,              -- 1-bit output: Programmable Full: This signal is asserted when the
+                                      -- number of words in the FIFO is greater than or equal to the
+                                      -- programmable full threshold value. It is de-asserted when the number
+                                      -- of words in the FIFO is less than the programmable full threshold
+                                      -- value.
+
+      rd_data_count => OPEN,          -- RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates
+                                      -- the number of words read from the FIFO.
+
+      rd_rst_busy => OPEN,            -- 1-bit output: Read Reset Busy: Active-High indicator that the FIFO
+                                      -- read domain is currently in a reset state.
+
+      sbiterr => OPEN,                -- 1-bit output: Single Bit Error: Indicates that the ECC decoder
+                                      -- detected and fixed a single-bit error.
+
+      underflow => OPEN,              -- 1-bit output: Underflow: Indicates that the read request (rd_en)
+                                      -- during the previous clock cycle was rejected because the FIFO is
+                                      -- empty. Under flowing the FIFO is not destructive to the FIFO.
+
+      wr_ack => OPEN,                 -- 1-bit output: Write Acknowledge: This signal indicates that a write
+                                      -- request (wr_en) during the prior clock cycle is succeeded.
+
+      wr_data_count => usedw,         -- WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates
+                                      -- the number of words written into the FIFO.
+
+      wr_rst_busy => OPEN,            -- 1-bit output: Write Reset Busy: Active-High indicator that the FIFO
+                                      -- write domain is currently in a reset state.
+
+      din => data,                    -- WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when
+                                      -- writing the FIFO.
+
+      injectdbiterr => '0',           -- 1-bit input: Double Bit Error Injection: Injects a double bit error if
+                                      -- the ECC feature is used on block RAMs or UltraRAM macros.
+
+      injectsbiterr => '0',           -- 1-bit input: Single Bit Error Injection: Injects a single bit error if
+                                      -- the ECC feature is used on block RAMs or UltraRAM macros.
+
+      rd_en => rdreq,                 -- 1-bit input: Read Enable: If the FIFO is not empty, asserting this
+                                      -- signal causes data (on dout) to be read from the FIFO. Must be held
+                                      -- active-low when rd_rst_busy is active high.
+
+      rst => aclr,                    -- 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be
+                                      -- unstable at the time of applying reset, but reset must be released
+                                      -- only after the clock(s) is/are stable.
+
+      sleep => '0',                   -- 1-bit input: Dynamic power saving: If sleep is High, the memory/fifo
+                                      -- block is in power saving mode.
+
+      wr_clk => clock,                -- 1-bit input: Write clock: Used for write operation. wr_clk must be a
+                                      -- free running clock.
+
+      wr_en => wrreq                  -- 1-bit input: Write Enable: If the FIFO is not full, asserting this
+                                      -- signal causes data (on din) to be written to the FIFO. Must be held
+                                      -- active-low when rst or wr_rst_busy is active high.
+
+   );
+
+   -- End of xpm_fifo_async_inst instantiation
+
+END SYN;

libraries/technology/ip_ultrascale/ram/hdllib.cfg

@@ -11,7 +11,7 @@ synth_files =
     
 #    ip_ultrascale_ram_crwk_crw.vhd
     ip_ultrascale_ram_crw_crw.vhd
-#    ip_ultrascale_ram_cr_cw.vhd
+    ip_ultrascale_ram_cr_cw.vhd
 #    ip_ultrascale_ram_r_w.vhd
     
 test_bench_files =