added XMP templates for ip_ultrascale_ram

libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd

@@ -21,22 +21,21 @@
 
 -- RadioHDL wrapper
 
-LIBRARY ieee, technology_lib;
+LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 USE ieee.numeric_std.all;
-USE technology_lib.technology_pkg.all;
 
-LIBRARY altera_lnsim;
-USE altera_lnsim.altera_lnsim_components.all;
+LIBRARY xpm;
+USE xpm.vcomponents.ALL;
 
-ENTITY ip_arria10_e2sg_ram_cr_cw IS
+ENTITY ip_ultrascale_ram_cr_cw IS
   GENERIC (
     g_inferred   : BOOLEAN := FALSE;
     g_adr_w      : NATURAL := 5;
     g_dat_w      : NATURAL := 8;
     g_nof_words  : NATURAL := 2**5;
     g_rd_latency : NATURAL := 1;  -- choose 1 or 2
-    g_init_file  : STRING  := "UNUSED"
+    g_init_file  : STRING  := "none"
   );
   PORT
   (
@@ -48,115 +47,122 @@ ENTITY ip_arria10_e2sg_ram_cr_cw IS
     wren      : IN  STD_LOGIC  := '0';
     q         : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
   );
-END ip_arria10_e2sg_ram_cr_cw;
+END ip_ultrascale_ram_cr_cw;
 
 
-ARCHITECTURE SYN OF ip_arria10_e2sg_ram_cr_cw IS
+ARCHITECTURE SYN OF ip_ultrascale_ram_cr_cw IS
 
-  CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
-
-  COMPONENT altera_syncram
-  GENERIC (
-          address_aclr_b  : string;
-          address_reg_b  : string;
-          clock_enable_input_a  : string;
-          clock_enable_input_b  : string;
-          clock_enable_output_b  : string;
-          init_file  : string;
-          intended_device_family  : string;
-          lpm_type  : string;
-          numwords_a  : integer;
-          numwords_b  : integer;
-          operation_mode  : string;
-          outdata_aclr_b  : string;
-          outdata_reg_b  : string;
-          power_up_uninitialized  : string;
-          read_during_write_mode_mixed_ports : string;
-          widthad_a  : integer;
-          widthad_b  : integer;
-          width_a  : integer;
-          width_b  : integer;
-          width_byteena_a  : integer
-  );
-  PORT (
-      address_a : in std_logic_vector(g_adr_w-1 downto 0);
-      address_b : in std_logic_vector(g_adr_w-1 downto 0);
-      clock0 : in std_logic;
-      clock1 : in std_logic;
-      data_a : in std_logic_vector(g_dat_w-1 downto 0);
-      wren_a : in std_logic;
-      q_b : out std_logic_vector(g_dat_w-1 downto 0)
-  );
-  END COMPONENT;
-  
-  SIGNAL rdaddr : natural range 0 to g_nof_words - 1;
-  SIGNAL wraddr : natural range 0 to g_nof_words - 1;
-  
-  SIGNAL out_q  : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
-  SIGNAL reg_q  : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
-  
 BEGIN
 
-  ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e2sg_ram_cr_cw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
-  
-  gen_ip : IF g_inferred=FALSE GENERATE
-    -- Copied from ip_arria10_e2sg_ram_cr_cw/ram_2port_140/sim/ip_arria10_e2sg_ram_cr_cw_ram_2port_140_72tpmcy.vhd
-    u_altera_syncram : altera_syncram
-    GENERIC MAP (
-            address_aclr_b  => "NONE",
-            address_reg_b  => "CLOCK1",
-            clock_enable_input_a  => "BYPASS",
-            clock_enable_input_b  => "BYPASS",
-            clock_enable_output_b  => "BYPASS",
-            init_file  => g_init_file,
-            intended_device_family  => "Arria 10",
-            lpm_type  => "altera_syncram",
-            numwords_a  => g_nof_words,
-            numwords_b  => g_nof_words,
-            operation_mode  => "DUAL_PORT",
-            outdata_aclr_b  => "NONE",
-            outdata_reg_b  => c_outdata_reg_b,
-            power_up_uninitialized  => "FALSE",
-            read_during_write_mode_mixed_ports => "OLD_DATA",
-            widthad_a  => g_adr_w,
-            widthad_b  => g_adr_w,
-            width_a  => g_dat_w,
-            width_b  => g_dat_w,
-            width_byteena_a  => 1
-    )
-    PORT MAP (
-        address_a => wraddress,
-        address_b => rdaddress,
-        clock0 => wrclk,
-        clock1 => rdclk,
-        data_a => data,
-        wren_a => wren,
-        q_b => q
-    );
-  END GENERATE;
-  
-  gen_inferred : IF g_inferred=TRUE GENERATE
-    rdaddr <= TO_INTEGER(UNSIGNED(rdaddress));
-    wraddr <= TO_INTEGER(UNSIGNED(wraddress));
-    
-    u_mem : entity work.ip_arria10_e2sg_simple_dual_port_ram_dual_clock
-    generic map (
-      DATA_WIDTH => g_dat_w,
-      ADDR_WIDTH => g_adr_w
-    )
-    port map (
-      rclk  => rdclk,
-      wclk  => wrclk,
-      raddr => rdaddr,
-      waddr => wraddr,
-      data  => data,
-      we    => wren,
-      q     => out_q
-    );
-  
-    reg_q <= out_q WHEN rising_edge(rdclk);
-    
-    q <= out_q WHEN g_rd_latency=1 ELSE reg_q;  
-  END GENERATE;
+  ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_ultrascale_ram_cr_cw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
   
+  ASSERT g_inferred=FALSE REPORT "ip_ultrascale_ram_crw_crw : cannot infer RAM" SEVERITY FAILURE;
+
+   -- xpm_memory_sdpram: Simple Dual Port RAM
+   -- Xilinx Parameterized Macro, version 2022.1
+   xpm_memory_sdpram_inst : xpm_memory_sdpram
+   generic map (
+      ADDR_WIDTH_A => g_adr_w,              -- DECIMAL
+      ADDR_WIDTH_B => g_adr_w,              -- DECIMAL
+      AUTO_SLEEP_TIME => 0,                 -- DECIMAL
+      BYTE_WRITE_WIDTH_A => 32,             -- DECIMAL
+      CASCADE_HEIGHT => 0,                  -- DECIMAL
+      CLOCKING_MODE => "independent_clock", -- String
+      ECC_MODE => "no_ecc",                 -- String
+      MEMORY_INIT_FILE => g_init_file,      -- String
+      MEMORY_INIT_PARAM => "0",             -- String
+      MEMORY_OPTIMIZATION => "true",        -- String
+      MEMORY_PRIMITIVE => "auto",           -- String
+      MEMORY_SIZE => g_nof_words,           -- DECIMAL
+      MESSAGE_CONTROL => 0,                 -- DECIMAL
+      READ_DATA_WIDTH_B => g_dat_w,         -- DECIMAL
+      READ_LATENCY_B => g_rd_latency,       -- DECIMAL
+      READ_RESET_VALUE_B => "0",            -- String
+      RST_MODE_A => "SYNC",                 -- String
+      RST_MODE_B => "SYNC",                 -- String
+      SIM_ASSERT_CHK => 0,                  -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      USE_EMBEDDED_CONSTRAINT => 0,         -- DECIMAL
+      USE_MEM_INIT => 1,                    -- DECIMAL
+      USE_MEM_INIT_MMI => 0,                -- DECIMAL
+      WAKEUP_TIME => "disable_sleep",       -- String
+      WRITE_DATA_WIDTH_A => g_dat_w,        -- DECIMAL
+      WRITE_MODE_B => "no_change",          -- String
+      WRITE_PROTECT => 1                    -- DECIMAL
+   )
+   port map (
+      dbiterra => OPEN,                 -- 1-bit output: Status signal to indicate double bit error occurrence
+                                        -- on the data output of port A.
+
+      dbiterrb => OPEN,                 -- 1-bit output: Status signal to indicate double bit error occurrence
+                                        -- on the data output of port A.
+
+      doutb => q,                       -- READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
+      sbiterra => OPEN,                 -- 1-bit output: Status signal to indicate single bit error occurrence
+                                        -- on the data output of port A.
+
+      sbiterrb => OPEN,                 -- 1-bit output: Status signal to indicate single bit error occurrence
+                                        -- on the data output of port B.
+
+      addra => wraddress,               -- ADDR_WIDTH_A-bit input: Address for port A write and read operations.
+      addrb => rdaddress,               -- ADDR_WIDTH_B-bit input: Address for port B write and read operations.
+      clka => wrclk,                    -- 1-bit input: Clock signal for port A. Also clocks port B when
+                                        -- parameter CLOCKING_MODE is "common_clock".
+
+      clkb => rdclk,                    -- 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
+                                        -- "independent_clock". Unused when parameter CLOCKING_MODE is
+                                        -- "common_clock".
+
+      dina => data,                     -- WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
+      ena => '1',                       -- 1-bit input: Memory enable signal for port A. Must be high on clock
+                                        -- cycles when read or write operations are initiated. Pipelined
+                                        -- internally.
+
+      enb => '1',                       -- 1-bit input: Memory enable signal for port B. Must be high on clock
+                                        -- cycles when read or write operations are initiated. Pipelined
+                                        -- internally.
+                                              
+      injectdbiterra => '0',            -- 1-bit input: Controls double bit error injection on input data when
+                                        -- ECC enabled (Error injection capability is not available in
+                                        -- "decode_only" mode).
+
+      injectdbiterrb => '0',            -- 1-bit input: Controls double bit error injection on input data when
+                                        -- ECC enabled (Error injection capability is not available in
+                                        -- "decode_only" mode).
+
+      injectsbiterra => '0',            -- 1-bit input: Controls single bit error injection on input data when
+                                        -- ECC enabled (Error injection capability is not available in
+                                        -- "decode_only" mode).
+
+      injectsbiterrb => '0',            -- 1-bit input: Controls single bit error injection on input data when
+                                        -- ECC enabled (Error injection capability is not available in
+                                        -- "decode_only" mode).
+
+      regcea => '1',                    -- 1-bit input: Clock Enable for the last register stage on the output
+                                        -- data path.
+
+      regceb => '1',                    -- 1-bit input: Clock Enable for the last register stage on the output
+                                        -- data path.
+
+      rsta => '0',                      -- 1-bit input: Reset signal for the final port A output register
+                                        -- stage. Synchronously resets output port douta to the value specified
+                                        -- by parameter READ_RESET_VALUE_A.
+
+      rstb => '0',                      -- 1-bit input: Reset signal for the final port B output register
+                                        -- stage. Synchronously resets output port doutb to the value specified
+                                        -- by parameter READ_RESET_VALUE_B.
+
+      sleep => '0',                     -- 1-bit input: sleep signal to enable the dynamic power saving feature.
+
+      wea => STD_LOGIC_VECTOR(wren),    -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
+                                        -- for port A input data port dina. 1 bit wide when word-wide writes
+                                        -- are used. In byte-wide write configurations, each bit controls the
+                                        -- writing one byte of dina to address addra. For example, to
+                                        -- synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
+                                        -- is 32, wea would be 4'b0010.
+
+   );
+
+   -- End of xpm_memory_sdpram_inst instantiation
+
+
 END SYN;

libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd

 -------------------------------------------------------------------------------
 --
--- Copyright (C) 2014
+-- Copyright (C) 2023
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
@@ -21,10 +21,12 @@
 
 -- RadioHDL wrapper
 
-LIBRARY ieee, technology_lib;
+LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 USE ieee.numeric_std.all;
-USE technology_lib.technology_pkg.all;
+  
+LIBRARY xpm;
+USE xpm.vcomponents.ALL;
 
 ENTITY ip_ultrascale_ram_crw_crw IS
   GENERIC (
@@ -33,7 +35,7 @@ ENTITY ip_ultrascale_ram_crw_crw IS
     g_dat_w      : NATURAL := 8;
     g_nof_words  : NATURAL := 2**5;
     g_rd_latency : NATURAL := 1;  -- choose 1 or 2
-    g_init_file  : STRING  := "UNUSED"
+    g_init_file  : STRING  := "none"
   );
   PORT
   (
@@ -51,286 +53,132 @@ ENTITY ip_ultrascale_ram_crw_crw IS
 END ip_ultrascale_ram_crw_crw;
 
 
-ARCHITECTURE ip_ultrascale_ram_crw_crw_arch OF ip_ultrascale_ram_crw_crw IS
-  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
-  ATTRIBUTE DowngradeIPIdentifiedWarnings OF ip_ultrascale_ram_crw_crw_arch: ARCHITECTURE IS "yes";
-  COMPONENT blk_mem_gen_v8_4_5 IS
-    GENERIC (
-      C_FAMILY : STRING;
-      C_XDEVICEFAMILY : STRING;
-      C_ELABORATION_DIR : STRING;
-      C_INTERFACE_TYPE : INTEGER;
-      C_AXI_TYPE : INTEGER;
-      C_AXI_SLAVE_TYPE : INTEGER;
-      C_USE_BRAM_BLOCK : INTEGER;
-      C_ENABLE_32BIT_ADDRESS : INTEGER;
-      C_CTRL_ECC_ALGO : STRING;
-      C_HAS_AXI_ID : INTEGER;
-      C_AXI_ID_WIDTH : INTEGER;
-      C_MEM_TYPE : INTEGER;
-      C_BYTE_SIZE : INTEGER;
-      C_ALGORITHM : INTEGER;
-      C_PRIM_TYPE : INTEGER;
-      C_LOAD_INIT_FILE : INTEGER;
-      C_INIT_FILE_NAME : STRING;
-      C_INIT_FILE : STRING;
-      C_USE_DEFAULT_DATA : INTEGER;
-      C_DEFAULT_DATA : STRING;
-      C_HAS_RSTA : INTEGER;
-      C_RST_PRIORITY_A : STRING;
-      C_RSTRAM_A : INTEGER;
-      C_INITA_VAL : STRING;
-      C_HAS_ENA : INTEGER;
-      C_HAS_REGCEA : INTEGER;
-      C_USE_BYTE_WEA : INTEGER;
-      C_WEA_WIDTH : INTEGER;
-      C_WRITE_MODE_A : STRING;
-      C_WRITE_WIDTH_A : INTEGER;
-      C_READ_WIDTH_A : INTEGER;
-      C_WRITE_DEPTH_A : INTEGER;
-      C_READ_DEPTH_A : INTEGER;
-      C_ADDRA_WIDTH : INTEGER;
-      C_HAS_RSTB : INTEGER;
-      C_RST_PRIORITY_B : STRING;
-      C_RSTRAM_B : INTEGER;
-      C_INITB_VAL : STRING;
-      C_HAS_ENB : INTEGER;
-      C_HAS_REGCEB : INTEGER;
-      C_USE_BYTE_WEB : INTEGER;
-      C_WEB_WIDTH : INTEGER;
-      C_WRITE_MODE_B : STRING;
-      C_WRITE_WIDTH_B : INTEGER;
-      C_READ_WIDTH_B : INTEGER;
-      C_WRITE_DEPTH_B : INTEGER;
-      C_READ_DEPTH_B : INTEGER;
-      C_ADDRB_WIDTH : INTEGER;
-      C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
-      C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
-      C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
-      C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
-      C_MUX_PIPELINE_STAGES : INTEGER;
-      C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
-      C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
-      C_USE_SOFTECC : INTEGER;
-      C_USE_ECC : INTEGER;
-      C_EN_ECC_PIPE : INTEGER;
-      C_READ_LATENCY_A : INTEGER;
-      C_READ_LATENCY_B : INTEGER;
-      C_HAS_INJECTERR : INTEGER;
-      C_SIM_COLLISION_CHECK : STRING;
-      C_COMMON_CLK : INTEGER;
-      C_DISABLE_WARN_BHV_COLL : INTEGER;
-      C_EN_SLEEP_PIN : INTEGER;
-      C_USE_URAM : INTEGER;
-      C_EN_RDADDRA_CHG : INTEGER;
-      C_EN_RDADDRB_CHG : INTEGER;
-      C_EN_DEEPSLEEP_PIN : INTEGER;
-      C_EN_SHUTDOWN_PIN : INTEGER;
-      C_EN_SAFETY_CKT : INTEGER;
-      C_DISABLE_WARN_BHV_RANGE : INTEGER;
-      C_COUNT_36K_BRAM : STRING;
-      C_COUNT_18K_BRAM : STRING;
-      C_EST_POWER_SUMMARY : STRING
-    );
-    PORT (
-      clka : IN STD_LOGIC;
-      rsta : IN STD_LOGIC;
-      ena : IN STD_LOGIC;
-      regcea : IN STD_LOGIC;
-      wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-      addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
-      dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-      douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-      clkb : IN STD_LOGIC;
-      rstb : IN STD_LOGIC;
-      enb : IN STD_LOGIC;
-      regceb : IN STD_LOGIC;
-      web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-      addrb : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
-      dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-      doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-      injectsbiterr : IN STD_LOGIC;
-      injectdbiterr : IN STD_LOGIC;
-      eccpipece : IN STD_LOGIC;
-      sbiterr : OUT STD_LOGIC;
-      dbiterr : OUT STD_LOGIC;
-      rdaddrecc : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
-      sleep : IN STD_LOGIC;
-      deepsleep : IN STD_LOGIC;
-      shutdown : IN STD_LOGIC;
-      rsta_busy : OUT STD_LOGIC;
-      rstb_busy : OUT STD_LOGIC;
-      s_aclk : IN STD_LOGIC;
-      s_aresetn : IN STD_LOGIC;
-      s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-      s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-      s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-      s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
-      s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
-      s_axi_awvalid : IN STD_LOGIC;
-      s_axi_awready : OUT STD_LOGIC;
-      s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-      s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-      s_axi_wlast : IN STD_LOGIC;
-      s_axi_wvalid : IN STD_LOGIC;
-      s_axi_wready : OUT STD_LOGIC;
-      s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
-      s_axi_bvalid : OUT STD_LOGIC;
-      s_axi_bready : IN STD_LOGIC;
-      s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-      s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-      s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-      s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
-      s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
-      s_axi_arvalid : IN STD_LOGIC;
-      s_axi_arready : OUT STD_LOGIC;
-      s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-      s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
-      s_axi_rlast : OUT STD_LOGIC;
-      s_axi_rvalid : OUT STD_LOGIC;
-      s_axi_rready : IN STD_LOGIC;
-      s_axi_injectsbiterr : IN STD_LOGIC;
-      s_axi_injectdbiterr : IN STD_LOGIC;
-      s_axi_sbiterr : OUT STD_LOGIC;
-      s_axi_dbiterr : OUT STD_LOGIC;
-      s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
-    );
-  END COMPONENT blk_mem_gen_v8_4_5;
-  ATTRIBUTE X_CORE_INFO : STRING;
-  ATTRIBUTE X_CORE_INFO OF ip_ultrascale_ram_crw_crw_arch: ARCHITECTURE IS "blk_mem_gen_v8_4_5,Vivado 2022.1";
-  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
-  ATTRIBUTE CHECK_LICENSE_TYPE OF ip_ultrascale_ram_crw_crw_arch : ARCHITECTURE IS "ip_ultrascale_ram_crw_crw,blk_mem_gen_v8_4_5,{}";
+ARCHITECTURE SYN OF ip_ultrascale_ram_crw_crw IS
   
 BEGIN
 
-  ASSERT g_rd_latency=1   REPORT "ip_ultrascale_ram_crw_crw : read latency must be 1 (default)" SEVERITY FAILURE;
+  ASSERT g_rd_latency=1 OR g_rd_latency=2  REPORT "ip_ultrascale_ram_crw_crw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
   ASSERT g_inferred=FALSE REPORT "ip_ultrascale_ram_crw_crw : cannot infer RAM" SEVERITY FAILURE;
   
-  U0 : blk_mem_gen_v8_4_5
-    GENERIC MAP (
-      C_FAMILY => "virtexuplusHBM",
-      C_XDEVICEFAMILY => "virtexuplusHBM",
-      C_ELABORATION_DIR => "./",
-      C_INTERFACE_TYPE => 0,
-      C_AXI_TYPE => 1,
-      C_AXI_SLAVE_TYPE => 0,
-      C_USE_BRAM_BLOCK => 0,
-      C_ENABLE_32BIT_ADDRESS => 0,
-      C_CTRL_ECC_ALGO => "NONE",
-      C_HAS_AXI_ID => 0,
-      C_AXI_ID_WIDTH => 4,
-      C_MEM_TYPE => 2,
-      C_BYTE_SIZE => 9,
-      C_ALGORITHM => 1,
-      C_PRIM_TYPE => 1,
-      C_LOAD_INIT_FILE => 0,
-      C_INIT_FILE_NAME => "init_file",
-      C_INIT_FILE => g_init_file,
-      C_USE_DEFAULT_DATA => 0,
-      C_DEFAULT_DATA => "0",
-      C_HAS_RSTA => 0,
-      C_RST_PRIORITY_A => "CE",
-      C_RSTRAM_A => 0,
-      C_INITA_VAL => "0",
-      C_HAS_ENA => 1,
-      C_HAS_REGCEA => 0,
-      C_USE_BYTE_WEA => 0,
-      C_WEA_WIDTH => 1,
-      C_WRITE_MODE_A => "WRITE_FIRST",
-      C_WRITE_WIDTH_A => g_dat_w,
-      C_READ_WIDTH_A => g_dat_w,
-      C_WRITE_DEPTH_A => g_nof_words,
-      C_READ_DEPTH_A => g_nof_words,
-      C_ADDRA_WIDTH => g_adr_w,
-      C_HAS_RSTB => 0,
-      C_RST_PRIORITY_B => "CE",
-      C_RSTRAM_B => 0,
-      C_INITB_VAL => "0",
-      C_HAS_ENB => 1,
-      C_HAS_REGCEB => 0,
-      C_USE_BYTE_WEB => 0,
-      C_WEB_WIDTH => 1,
-      C_WRITE_MODE_B => "WRITE_FIRST",
-      C_WRITE_WIDTH_B => g_dat_w,
-      C_READ_WIDTH_B => g_dat_w,
-      C_WRITE_DEPTH_B => g_nof_words,
-      C_READ_DEPTH_B => g_nof_words,
-      C_ADDRB_WIDTH => g_adr_w,
-      C_HAS_MEM_OUTPUT_REGS_A => 1,
-      C_HAS_MEM_OUTPUT_REGS_B => 1,
-      C_HAS_MUX_OUTPUT_REGS_A => 0,
-      C_HAS_MUX_OUTPUT_REGS_B => 0,
-      C_MUX_PIPELINE_STAGES => 0,
-      C_HAS_SOFTECC_INPUT_REGS_A => 0,
-      C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
-      C_USE_SOFTECC => 0,
-      C_USE_ECC => 0,
-      C_EN_ECC_PIPE => 0,
-      C_READ_LATENCY_A => 1,
-      C_READ_LATENCY_B => 1,
-      C_HAS_INJECTERR => 0,
-      C_SIM_COLLISION_CHECK => "ALL",
-      C_COMMON_CLK => 0,
-      C_DISABLE_WARN_BHV_COLL => 0,
-      C_EN_SLEEP_PIN => 0,
-      C_USE_URAM => 0,
-      C_EN_RDADDRA_CHG => 0,
-      C_EN_RDADDRB_CHG => 0,
-      C_EN_DEEPSLEEP_PIN => 0,
-      C_EN_SHUTDOWN_PIN => 0,
-      C_EN_SAFETY_CKT => 0,
-      C_DISABLE_WARN_BHV_RANGE => 0,
-      C_COUNT_36K_BRAM => "NaN",
-      C_COUNT_18K_BRAM => "NaN",
-      C_EST_POWER_SUMMARY => "Estimated Power for IP     :     UNKNOWN"
-    )
-    PORT MAP (
-      clka => clk_a,
-      rsta => '0',
-      ena => '1',
-      regcea => '0',
-      wea(0) => wren_a,
-      addra => address_a,
-      dina => data_a,
-      douta => q_a,
-      clkb => clk_b,
-      rstb => '0',
-      enb => '1',
-      regceb => '0',
-      web(0) => wren_b,
-      addrb => address_b,
-      dinb => data_b,
-      doutb => q_b,
-      injectsbiterr => '0',
-      injectdbiterr => '0',
-      eccpipece => '0',
-      sleep => '0',
-      deepsleep => '0',
-      shutdown => '0',
-      s_aclk => '0',
-      s_aresetn => '0',
-      s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-      s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
-      s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-      s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-      s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-      s_axi_awvalid => '0',
-      s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-      s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-      s_axi_wlast => '0',
-      s_axi_wvalid => '0',
-      s_axi_bready => '0',
-      s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-      s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
-      s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-      s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-      s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-      s_axi_arvalid => '0',
-      s_axi_rready => '0',
-      s_axi_injectsbiterr => '0',
-      s_axi_injectdbiterr => '0'
-    );
+   -- xpm_memory_tdpram: True Dual Port RAM
+   -- Xilinx Parameterized Macro, version 2022.1
+
+   xpm_memory_tdpram_inst : xpm_memory_tdpram
+   generic map (
+      ADDR_WIDTH_A => g_adr_w,               -- DECIMAL
+      ADDR_WIDTH_B => g_adr_w,               -- DECIMAL
+      AUTO_SLEEP_TIME => 0,            -- DECIMAL
+      BYTE_WRITE_WIDTH_A => g_dat_w,        -- DECIMAL
+      BYTE_WRITE_WIDTH_B => g_dat_w,        -- DECIMAL
+      CASCADE_HEIGHT => 0,             -- DECIMAL
+      CLOCKING_MODE => "independent_clock", -- String
+      ECC_MODE => "no_ecc",            -- String
+      MEMORY_INIT_FILE => g_init_file,      -- String
+      MEMORY_INIT_PARAM => "0",        -- String
+      MEMORY_OPTIMIZATION => "true",   -- String
+      MEMORY_PRIMITIVE => "block",      -- String
+      MEMORY_SIZE => g_nof_words,             -- DECIMAL
+      MESSAGE_CONTROL => 0,            -- DECIMAL
+      READ_DATA_WIDTH_A => g_dat_w,         -- DECIMAL
+      READ_DATA_WIDTH_B => g_dat_w,         -- DECIMAL
+      READ_LATENCY_A => g_rd_latency,   -- DECIMAL
+      READ_LATENCY_B => g_rd_latency,   -- DECIMAL
+      READ_RESET_VALUE_A => "0",       -- String
+      READ_RESET_VALUE_B => "0",       -- String
+      RST_MODE_A => "SYNC",            -- String
+      RST_MODE_B => "SYNC",            -- String
+      SIM_ASSERT_CHK => 0,             -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+      USE_EMBEDDED_CONSTRAINT => 0,    -- DECIMAL
+      USE_MEM_INIT => 1,               -- DECIMAL
+      USE_MEM_INIT_MMI => 0,           -- DECIMAL
+      WAKEUP_TIME => "disable_sleep",  -- String
+      WRITE_DATA_WIDTH_A => g_dat_w,   -- DECIMAL
+      WRITE_DATA_WIDTH_B => g_dat_w,   -- DECIMAL
+      WRITE_MODE_A => "no_change",     -- String
+      WRITE_MODE_B => "no_change",     -- String
+      WRITE_PROTECT => 1               -- DECIMAL
+   )
+   port map (
+      dbiterra => OPEN,                 -- 1-bit output: Status signal to indicate double bit error occurrence
+                                        -- on the data output of port A.
+
+      dbiterrb => OPEN,                 -- 1-bit output: Status signal to indicate double bit error occurrence
+                                        -- on the data output of port A.
+
+      douta => q_a,                     -- READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
+      doutb => q_b,                     -- READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
+      sbiterra => OPEN,                 -- 1-bit output: Status signal to indicate single bit error occurrence
+                                        -- on the data output of port A.
+
+      sbiterrb => OPEN,                 -- 1-bit output: Status signal to indicate single bit error occurrence
+                                        -- on the data output of port B.
+
+      addra => address_a,               -- ADDR_WIDTH_A-bit input: Address for port A write and read operations.
+      addrb => address_b,               -- ADDR_WIDTH_B-bit input: Address for port B write and read operations.
+      clka => clk_a,                    -- 1-bit input: Clock signal for port A. Also clocks port B when
+                                        -- parameter CLOCKING_MODE is "common_clock".
+
+      clkb => clk_b,                    -- 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
+                                        -- "independent_clock". Unused when parameter CLOCKING_MODE is
+                                        -- "common_clock".
+
+      dina => data_a,                     -- WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
+      dinb => data_b,                     -- WRITE_DATA_WIDTH_B-bit input: Data input for port B write operations.
+      ena => '1',                       -- 1-bit input: Memory enable signal for port A. Must be high on clock
+                                        -- cycles when read or write operations are initiated. Pipelined
+                                        -- internally.
+
+      enb => '1',                       -- 1-bit input: Memory enable signal for port B. Must be high on clock
+                                        -- cycles when read or write operations are initiated. Pipelined
+                                        -- internally.
+                                              
+      injectdbiterra => '0',            -- 1-bit input: Controls double bit error injection on input data when
+                                        -- ECC enabled (Error injection capability is not available in
+                                        -- "decode_only" mode).
+
+      injectdbiterrb => '0',            -- 1-bit input: Controls double bit error injection on input data when
+                                        -- ECC enabled (Error injection capability is not available in
+                                        -- "decode_only" mode).
+
+      injectsbiterra => '0',            -- 1-bit input: Controls single bit error injection on input data when
+                                        -- ECC enabled (Error injection capability is not available in
+                                        -- "decode_only" mode).
+
+      injectsbiterrb => '0',            -- 1-bit input: Controls single bit error injection on input data when
+                                        -- ECC enabled (Error injection capability is not available in
+                                        -- "decode_only" mode).
+
+      regcea => '1',                    -- 1-bit input: Clock Enable for the last register stage on the output
+                                        -- data path.
+
+      regceb => '1',                    -- 1-bit input: Clock Enable for the last register stage on the output
+                                        -- data path.
+
+      rsta => '0',                      -- 1-bit input: Reset signal for the final port A output register
+                                        -- stage. Synchronously resets output port douta to the value specified
+                                        -- by parameter READ_RESET_VALUE_A.
+
+      rstb => '0',                      -- 1-bit input: Reset signal for the final port B output register
+                                        -- stage. Synchronously resets output port doutb to the value specified
+                                        -- by parameter READ_RESET_VALUE_B.
+
+      sleep => '0',                     -- 1-bit input: sleep signal to enable the dynamic power saving feature.
+      wea => STD_LOGIC_VECTOR(wren_a),                       -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
+                                        -- for port A input data port dina. 1 bit wide when word-wide writes
+                                        -- are used. In byte-wide write configurations, each bit controls the
+                                        -- writing one byte of dina to address addra. For example, to
+                                        -- synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
+                                        -- is 32, wea would be 4'b0010.
+
+      web => STD_LOGIC_VECTOR(wren_a)                        -- WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B-bit input: Write enable vector
+                                        -- for port B input data port dinb. 1 bit wide when word-wide writes
+                                        -- are used. In byte-wide write configurations, each bit controls the
+                                        -- writing one byte of dinb to address addrb. For example, to
+                                        -- synchronously write only bits [15-8] of dinb when WRITE_DATA_WIDTH_B
+                                        -- is 32, web would be 4'b0010.
+
+   );
 
-END ip_ultrascale_ram_crw_crw_arch;
+   -- End of xpm_memory_tdpram_inst instantiation
+				
+END SYN;