Skip to content
GitLab
Explore
Sign in
Register
Primary navigation
Search or go to…
Project
H
HDL
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Iterations
Wiki
Requirements
Jira
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Locked files
Build
Pipelines
Jobs
Pipeline schedules
Test cases
Artifacts
Deploy
Releases
Container Registry
Model registry
Operate
Environments
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Code review analytics
Issue analytics
Insights
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
RTSD
HDL
Commits
de677b66
Commit
de677b66
authored
2 years ago
by
Eric Kooistra
Browse files
Options
Downloads
Patches
Plain Diff
Added comment.
parent
d2e1f4e6
No related branches found
No related tags found
1 merge request
!258
Shortened sync interval and used pps_rst to make the tb simulate faster (few...
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
libraries/technology/jesd204b/tb_tech_jesd204b.vhd
+1
-0
1 addition, 0 deletions
libraries/technology/jesd204b/tb_tech_jesd204b.vhd
with
1 addition
and
0 deletions
libraries/technology/jesd204b/tb_tech_jesd204b.vhd
+
1
−
0
View file @
de677b66
...
...
@@ -216,6 +216,7 @@ BEGIN
p_monitor_jesd204b
:
PROCESS
BEGIN
-- Wait until after MM interface reset_out5 = rx_avs_rst_arr in ip_arria10_e2sg_jesd204b has been released
WAIT
UNTIL
sim_done
=
'1'
;
proc_common_wait_some_cycles
(
mm_clk
,
1
);
-- align with mm_clk domain
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment