corrected address width

libraries/technology/tse/tech_tse_arria10.vhd

@@ -140,7 +140,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+      reg_addr       => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
@@ -216,7 +216,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+      reg_addr       => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),

libraries/technology/tse/tech_tse_arria10_e1sg.vhd

@@ -140,7 +140,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+      reg_addr       => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
@@ -216,7 +216,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+      reg_addr       => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),

libraries/technology/tse/tech_tse_arria10_e2sg.vhd

@@ -140,7 +140,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+      reg_addr       => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
@@ -216,7 +216,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+      reg_addr       => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),

libraries/technology/tse/tech_tse_arria10_e3sge3.vhd

@@ -140,7 +140,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+      reg_addr       => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
@@ -216,7 +216,7 @@ BEGIN
       reset          => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
       -- MM control interface
       clk            => mm_clk,
-      reg_addr       => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 0),
+      reg_addr       => mm_sla_in.address(c_tech_tse_reg_addr_w-1 DOWNTO 0),
       reg_data_out   => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
       reg_rd         => mm_sla_in.rd,
       reg_data_in    => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),