updated tech lib to support ultrascale ram IPs

libraries/technology/memory/tech_memory_component_pkg.vhd

@@ -526,7 +526,7 @@ PACKAGE tech_memory_component_pkg IS
     g_dat_w      : NATURAL := 8;
     g_nof_words  : NATURAL := 2**5;
     g_rd_latency : NATURAL := 1;  -- choose 1 or 2
-    g_init_file  : STRING  := "UNUSED"
+    g_init_file  : STRING  := "none"
   );
   PORT
   (
@@ -542,6 +542,26 @@ PACKAGE tech_memory_component_pkg IS
     q_b       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
   );
   END COMPONENT;
-  
+    
+  COMPONENT ip_ultrascale_ram_cr_cw IS
+  GENERIC (
+    g_inferred   : BOOLEAN := FALSE;
+    g_adr_w      : NATURAL := 5;
+    g_dat_w      : NATURAL := 8;
+    g_nof_words  : NATURAL := 2**5;
+    g_rd_latency : NATURAL := 1;  -- choose 1 or 2
+    g_init_file  : STRING  := "none"
+  );
+  PORT
+  (
+    data      : IN  STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdaddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    rdclk     : IN  STD_LOGIC ;
+    wraddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    wrclk     : IN  STD_LOGIC  := '1';
+    wren      : IN  STD_LOGIC  := '0';
+    q         : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+  );
+  END COMPONENT;
 
 END tech_memory_component_pkg;

libraries/technology/memory/tech_memory_ram_cr_cw.vhd

@@ -31,6 +31,7 @@ LIBRARY ip_arria10_ram_lib;
 LIBRARY ip_arria10_e3sge3_ram_lib;
 LIBRARY ip_arria10_e1sg_ram_lib;
 LIBRARY ip_arria10_e2sg_ram_lib;
+LIBRARY ip_ultrascale_ram_lib;
 
 ENTITY tech_memory_ram_cr_cw IS
   GENERIC (
@@ -87,5 +88,11 @@ BEGIN
     GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
     PORT MAP (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
   END GENERATE;
-  
+ 
+  gen_ip_ultrascale : IF g_technology=c_tech_ultrascale GENERATE
+    u0 : ip_ultrascale_ram_cr_cw
+    GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+    PORT MAP (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
+  END GENERATE; 
+
 END ARCHITECTURE;