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Commit 3ed294cf authored by Reinier van der Walle's avatar Reinier van der Walle
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corrected syntax

parent 56102f69
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1 merge request!327Resolve HPR-85
Pipeline #48083 passed
......@@ -153,7 +153,7 @@ BEGIN
sleep => '0', -- 1-bit input: sleep signal to enable the dynamic power saving feature.
wea => STD_LOGIC_VECTOR(wren), -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
wea(0) => wren, -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
-- for port A input data port dina. 1 bit wide when word-wide writes
-- are used. In byte-wide write configurations, each bit controls the
-- writing one byte of dina to address addra. For example, to
......
......@@ -163,14 +163,14 @@ BEGIN
-- by parameter READ_RESET_VALUE_B.
sleep => '0', -- 1-bit input: sleep signal to enable the dynamic power saving feature.
wea => STD_LOGIC_VECTOR(wren_a), -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
wea(0) => wren_a, -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
-- for port A input data port dina. 1 bit wide when word-wide writes
-- are used. In byte-wide write configurations, each bit controls the
-- writing one byte of dina to address addra. For example, to
-- synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
-- is 32, wea would be 4'b0010.
web => STD_LOGIC_VECTOR(wren_a) -- WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B-bit input: Write enable vector
web(0) => wren_a -- WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B-bit input: Write enable vector
-- for port B input data port dinb. 1 bit wide when word-wide writes
-- are used. In byte-wide write configurations, each bit controls the
-- writing one byte of dinb to address addrb. For example, to
......
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