Connect missing IN jesd204b_disable_arr.

libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd

@@ -59,7 +59,7 @@ ENTITY ip_arria10_e2sg_jesd204b IS
     -- MM Control
     mm_clk                : IN  STD_LOGIC;
     mm_rst                : IN  STD_LOGIC;
-    jesd204b_disable_arr  : IN  STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '0');
+    jesd204b_disable_arr  : IN  STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
          
     jesd204b_mosi         : IN  t_mem_mosi;         --  mm control
     jesd204b_miso         : OUT t_mem_miso; 

libraries/technology/jesd204b/tech_jesd204b.vhd

@@ -142,6 +142,8 @@ BEGIN
       jesd204b_sysref      => jesd204b_sysref,   
       jesd204b_sync_n_arr  => jesd204b_sync_n_arr,   
   
+      jesd204b_disable_arr => jesd204b_disable_arr,
+
       rx_src_out_arr       => rx_sosi_arr,
       rx_clk               => rx_clk,          
       rx_rst               => rx_rst,          

libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd

@@ -48,6 +48,8 @@ ENTITY tech_jesd204b_arria10_e2sg IS
     jesd204b_sysref       : IN STD_LOGIC := '0';                             -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk 
     jesd204b_sync_n_arr   : OUT STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0);   -- output to control ADC initialization/syncronization phase
     
+    jesd204b_disable_arr  : IN STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+
     -- Data to fabric
     rx_src_out_arr        : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);    -- Parallel data out to fabric
     rx_clk                : OUT  STD_LOGIC := '0';                           -- Exported data clock (frame clock) to fabric
@@ -83,6 +85,8 @@ BEGIN
     jesd204b_sysref      => jesd204b_sysref,   
     jesd204b_sync_n_arr  => jesd204b_sync_n_arr,   
 
+    jesd204b_disable_arr => jesd204b_disable_arr,
+
     rx_src_out_arr       => rx_src_out_arr,
     rx_clk               => rx_clk,          
     rx_rst               => rx_rst,