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RTSD
HDL
Commits
d06d23d4
Commit
d06d23d4
authored
2 years ago
by
Eric Kooistra
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Use word addresses and add more registers from registermap-jesd-rx.xlsx.
parent
e3dae31e
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!258
Shortened sync interval and used pps_rst to make the tb simulate faster (few...
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libraries/technology/jesd204b/registermap-jesd-rx.xlsx
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-0
0 additions, 0 deletions
libraries/technology/jesd204b/registermap-jesd-rx.xlsx
libraries/technology/jesd204b/tech_jesd204b_pkg.vhd
+16
-7
16 additions, 7 deletions
libraries/technology/jesd204b/tech_jesd204b_pkg.vhd
with
16 additions
and
7 deletions
libraries/technology/jesd204b/registermap-jesd-rx.xlsx
0 → 100644
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libraries/technology/jesd204b/tech_jesd204b_pkg.vhd
+
16
−
7
View file @
d06d23d4
...
@@ -16,15 +16,13 @@
...
@@ -16,15 +16,13 @@
-- See the License for the specific language governing permissions and
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- limitations under the License.
--
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- Author: E. Kooistra
-- Author: E. Kooistra
-- Purpose: Test bench parameters for the JESD204B IP.
-- Purpose: Test bench parameters for the JESD204B IP.
-- Description:
-- Description:
-- Remark:
-- Remark:
-- .
-- .
From registermap-jesd-rx.xlsx
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
LIBRARY
IEEE
,
technology_lib
;
LIBRARY
IEEE
,
technology_lib
;
...
@@ -36,19 +34,30 @@ PACKAGE tech_jesd204b_pkg IS
...
@@ -36,19 +34,30 @@ PACKAGE tech_jesd204b_pkg IS
CONSTANT
tech_jesd204b_port_span_w
:
NATURAL
:
=
8
;
CONSTANT
tech_jesd204b_port_span_w
:
NATURAL
:
=
8
;
CONSTANT
tech_jesd204b_port_span
:
NATURAL
:
=
2
**
tech_jesd204b_port_span_w
;
CONSTANT
tech_jesd204b_port_span
:
NATURAL
:
=
2
**
tech_jesd204b_port_span_w
;
CONSTANT
tech_jesd204b_field_rx_err0_adr
:
NATURAL
:
=
16
#
60
#
;
CONSTANT
tech_jesd204b_field_rx_syncn_sysref_ctrl_adr
:
NATURAL
:
=
16
#
54
#
/
4
;
CONSTANT
tech_jesd204b_field_rx_syncn_sysref_ctrl_link_reinit
:
NATURAL
:
=
1
;
CONSTANT
tech_jesd204b_field_rx_syncn_sysref_ctrl_singled
:
NATURAL
:
=
2
;
CONSTANT
tech_jesd204b_field_rx_syncn_sysref_ctrl_alwayson
:
NATURAL
:
=
4
;
CONSTANT
tech_jesd204b_field_rx_err0_adr
:
NATURAL
:
=
16
#
60
#
/
4
;
CONSTANT
tech_jesd204b_field_rx_err0_w
:
NATURAL
:
=
9
;
CONSTANT
tech_jesd204b_field_rx_err0_w
:
NATURAL
:
=
9
;
CONSTANT
tech_jesd204b_field_rx_err0_lo
:
NATURAL
:
=
0
;
CONSTANT
tech_jesd204b_field_rx_err0_lo
:
NATURAL
:
=
0
;
CONSTANT
tech_jesd204b_field_rx_err0_hi
:
NATURAL
:
=
tech_jesd204b_field_rx_err0_w
-1
+
tech_jesd204b_field_rx_err0_lo
;
CONSTANT
tech_jesd204b_field_rx_err0_hi
:
NATURAL
:
=
tech_jesd204b_field_rx_err0_w
-1
+
tech_jesd204b_field_rx_err0_lo
;
CONSTANT
tech_jesd204b_field_rx_err1_adr
:
NATURAL
:
=
16
#
64
#
;
CONSTANT
tech_jesd204b_field_rx_err1_adr
:
NATURAL
:
=
16
#
64
#
/
4
;
CONSTANT
tech_jesd204b_field_rx_err1_w
:
NATURAL
:
=
10
;
CONSTANT
tech_jesd204b_field_rx_err1_w
:
NATURAL
:
=
10
;
CONSTANT
tech_jesd204b_field_rx_err1_lo
:
NATURAL
:
=
0
;
CONSTANT
tech_jesd204b_field_rx_err1_lo
:
NATURAL
:
=
0
;
CONSTANT
tech_jesd204b_field_rx_err1_hi
:
NATURAL
:
=
tech_jesd204b_field_rx_err1_w
-1
+
tech_jesd204b_field_rx_err1_lo
;
CONSTANT
tech_jesd204b_field_rx_err1_hi
:
NATURAL
:
=
tech_jesd204b_field_rx_err1_w
-1
+
tech_jesd204b_field_rx_err1_lo
;
CONSTANT
tech_jesd204b_field_csr_rbd_count_adr
:
NATURAL
:
=
16
#
80
#
;
CONSTANT
tech_jesd204b_field_rx_err_enable_adr
:
NATURAL
:
=
16
#
74
#
/
4
;
CONSTANT
tech_jesd204b_field_rx_err_enable_reset
:
INTEGER
:
=
16
#
17
F9FE
#
;
CONSTANT
tech_jesd204b_field_rx_err_link_reinit_adr
:
NATURAL
:
=
16
#
78
#
/
4
;
CONSTANT
tech_jesd204b_field_rx_err_link_reinit_reset
:
INTEGER
:
=
16
#
3902
#
;
CONSTANT
tech_jesd204b_field_csr_rbd_count_adr
:
NATURAL
:
=
16
#
80
#
/
4
;
CONSTANT
tech_jesd204b_field_csr_rbd_count_w
:
NATURAL
:
=
8
;
CONSTANT
tech_jesd204b_field_csr_rbd_count_w
:
NATURAL
:
=
8
;
CONSTANT
tech_jesd204b_field_csr_rbd_count_lo
:
NATURAL
:
=
3
;
CONSTANT
tech_jesd204b_field_csr_rbd_count_lo
:
NATURAL
:
=
3
;
CONSTANT
tech_jesd204b_field_csr_rbd_count_hi
:
NATURAL
:
=
tech_jesd204b_field_csr_rbd_count_w
-1
+
tech_jesd204b_field_csr_rbd_count_lo
;
CONSTANT
tech_jesd204b_field_csr_rbd_count_hi
:
NATURAL
:
=
tech_jesd204b_field_csr_rbd_count_w
-1
+
tech_jesd204b_field_csr_rbd_count_lo
;
CONSTANT
tech_jesd204b_field_csr_dev_syncn_adr
:
NATURAL
:
=
16
#
80
#
;
CONSTANT
tech_jesd204b_field_csr_dev_syncn_adr
:
NATURAL
:
=
16
#
80
#
/
4
;
CONSTANT
tech_jesd204b_field_csr_dev_syncn_w
:
NATURAL
:
=
1
;
CONSTANT
tech_jesd204b_field_csr_dev_syncn_w
:
NATURAL
:
=
1
;
CONSTANT
tech_jesd204b_field_csr_dev_syncn_lo
:
NATURAL
:
=
0
;
CONSTANT
tech_jesd204b_field_csr_dev_syncn_lo
:
NATURAL
:
=
0
;
CONSTANT
tech_jesd204b_field_csr_dev_syncn_hi
:
NATURAL
:
=
tech_jesd204b_field_csr_dev_syncn_w
-1
+
tech_jesd204b_field_csr_dev_syncn_lo
;
CONSTANT
tech_jesd204b_field_csr_dev_syncn_hi
:
NATURAL
:
=
tech_jesd204b_field_csr_dev_syncn_w
-1
+
tech_jesd204b_field_csr_dev_syncn_lo
;
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