Use fractional PLL to created 156.25 MHz and 312.5 MHz for mac_10g and for 10gbase_r. The 10gbase_r XGMII interface is not available at 32b so need to stick to 64b@ 156.25MHz.

-Fixed address width assignment for data buffers.

-Connected reset conduit in qsys.

Added fPLL to generate 156.25 MHz and 312.5 MHz from 644.53125 MHz XO reference clock. Needed for 10G MAC and 10gbase_r with XGMII at 64bit.

Mentioned that set_modelsim is used in run_modelsim and similar set_quartus is used in run_quartus. Both are used in run_altera_simlib_comp.

Added description of tools/quartus/run_altera_simlib_comp for compiling the Altera libraries for simulation with Modelsim.

-Compiles OK in modelsim.

Added script for compiling the Altera simulation libraries to avoid having to use the Quartus GUI and to be able to keep on using 'mk all' in Modelsim.

Define set_modelsim and call it in run_modelsim, to have similar structure as with set_quartus and run_quartus.

-Added support for .vho files (TB files only);
-Updated hdltool_readme.txt accordingly.

 . Only the permutator and the multiplier stages are used
 . Block gens generate subband data from HEX files
   . Single amplitude
   . Phase offset 1 degree per incremental input
   . 1024 identical subbands per stream
 . Correlator multiplies using conjugate so we can extract the phase diffs
 . Data buffers are read out by tc_correlator.py 
   . Phase info is extracted and plotted
 . Current nof_inputs = 24.