pll to drive 156.25 and 312.5 MHz clocks for xgmii and mac

libraries/technology/ip_arria10/transceiver_phy_1/transceiver_phy_1.qsys

+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags="INTERNAL_COMPONENT=true"
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element $${FILENAME}
+   {
+   }
+   element transceiver_phy_inst
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115R2F40I2LG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="tx_analogreset"
+   internal="transceiver_phy_inst.tx_analogreset"
+   type="conduit"
+   dir="end">
+  <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+   name="tx_digitalreset"
+   internal="transceiver_phy_inst.tx_digitalreset"
+   type="conduit"
+   dir="end">
+  <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+   name="rx_analogreset"
+   internal="transceiver_phy_inst.rx_analogreset"
+   type="conduit"
+   dir="end">
+  <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+   name="rx_digitalreset"
+   internal="transceiver_phy_inst.rx_digitalreset"
+   type="conduit"
+   dir="end">
+  <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+   name="tx_cal_busy"
+   internal="transceiver_phy_inst.tx_cal_busy"
+   type="conduit"
+   dir="end">
+  <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+   name="rx_cal_busy"
+   internal="transceiver_phy_inst.rx_cal_busy"
+   type="conduit"
+   dir="end">
+  <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+   name="tx_serial_clk0"
+   internal="transceiver_phy_inst.tx_serial_clk0"
+   type="conduit"
+   dir="end">
+  <port name="tx_serial_clk0" internal="tx_serial_clk0" />
+ </interface>
+ <interface
+   name="rx_cdr_refclk0"
+   internal="transceiver_phy_inst.rx_cdr_refclk0"
+   type="conduit"
+   dir="end">
+  <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
+ </interface>
+ <interface
+   name="tx_serial_data"
+   internal="transceiver_phy_inst.tx_serial_data"
+   type="conduit"
+   dir="end">
+  <port name="tx_serial_data" internal="tx_serial_data" />
+ </interface>
+ <interface
+   name="rx_serial_data"
+   internal="transceiver_phy_inst.rx_serial_data"
+   type="conduit"
+   dir="end">
+  <port name="rx_serial_data" internal="rx_serial_data" />
+ </interface>
+ <interface
+   name="rx_is_lockedtodata"
+   internal="transceiver_phy_inst.rx_is_lockedtodata"
+   type="conduit"
+   dir="end">
+  <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+   name="tx_coreclkin"
+   internal="transceiver_phy_inst.tx_coreclkin"
+   type="conduit"
+   dir="end">
+  <port name="tx_coreclkin" internal="tx_coreclkin" />
+ </interface>
+ <interface
+   name="rx_coreclkin"
+   internal="transceiver_phy_inst.rx_coreclkin"
+   type="conduit"
+   dir="end">
+  <port name="rx_coreclkin" internal="rx_coreclkin" />
+ </interface>
+ <interface
+   name="tx_clkout"
+   internal="transceiver_phy_inst.tx_clkout"
+   type="conduit"
+   dir="end">
+  <port name="tx_clkout" internal="tx_clkout" />
+ </interface>
+ <interface
+   name="rx_clkout"
+   internal="transceiver_phy_inst.rx_clkout"
+   type="conduit"
+   dir="end">
+  <port name="rx_clkout" internal="rx_clkout" />
+ </interface>
+ <interface
+   name="tx_parallel_data"
+   internal="transceiver_phy_inst.tx_parallel_data"
+   type="conduit"
+   dir="end">
+  <port name="tx_parallel_data" internal="tx_parallel_data" />
+ </interface>
+ <interface
+   name="tx_control"
+   internal="transceiver_phy_inst.tx_control"
+   type="conduit"
+   dir="end">
+  <port name="tx_control" internal="tx_control" />
+ </interface>
+ <interface
+   name="tx_err_ins"
+   internal="transceiver_phy_inst.tx_err_ins"
+   type="conduit"
+   dir="end">
+  <port name="tx_err_ins" internal="tx_err_ins" />
+ </interface>
+ <interface
+   name="unused_tx_parallel_data"
+   internal="transceiver_phy_inst.unused_tx_parallel_data"
+   type="conduit"
+   dir="end">
+  <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
+ </interface>
+ <interface
+   name="unused_tx_control"
+   internal="transceiver_phy_inst.unused_tx_control"
+   type="conduit"
+   dir="end">
+  <port name="unused_tx_control" internal="unused_tx_control" />
+ </interface>
+ <interface
+   name="rx_parallel_data"
+   internal="transceiver_phy_inst.rx_parallel_data"
+   type="conduit"
+   dir="end">
+  <port name="rx_parallel_data" internal="rx_parallel_data" />
+ </interface>
+ <interface
+   name="rx_control"
+   internal="transceiver_phy_inst.rx_control"
+   type="conduit"
+   dir="end">
+  <port name="rx_control" internal="rx_control" />
+ </interface>
+ <interface
+   name="unused_rx_parallel_data"
+   internal="transceiver_phy_inst.unused_rx_parallel_data"
+   type="conduit"
+   dir="end">
+  <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
+ </interface>
+ <interface
+   name="unused_rx_control"
+   internal="transceiver_phy_inst.unused_rx_control"
+   type="conduit"
+   dir="end">
+  <port name="unused_rx_control" internal="unused_rx_control" />
+ </interface>
+ <interface
+   name="tx_enh_data_valid"
+   internal="transceiver_phy_inst.tx_enh_data_valid"
+   type="conduit"
+   dir="end">
+  <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
+ </interface>
+ <interface
+   name="rx_enh_data_valid"
+   internal="transceiver_phy_inst.rx_enh_data_valid"
+   type="conduit"
+   dir="end">
+  <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
+ </interface>
+ <interface
+   name="rx_enh_blk_lock"
+   internal="transceiver_phy_inst.rx_enh_blk_lock"
+   type="conduit"
+   dir="end">
+  <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
+ </interface>
+ <interface
+   name="tx_pma_div_clkout"
+   internal="transceiver_phy_inst.tx_pma_div_clkout"
+   type="conduit"
+   dir="end">
+  <port name="tx_pma_div_clkout" internal="tx_pma_div_clkout" />
+ </interface>
+ <interface
+   name="tx_pma_clkout"
+   internal="transceiver_phy_inst.tx_pma_clkout"
+   type="conduit"
+   dir="end">
+  <port name="tx_pma_clkout" internal="tx_pma_clkout" />
+ </interface>
+ <interface name="rx_pma_clkout" internal="transceiver_phy_inst.rx_pma_clkout" />
+ <interface
+   name="rx_pma_div_clkout"
+   internal="transceiver_phy_inst.rx_pma_div_clkout" />
+ <module
+   kind="altera_xcvr_native_a10"
+   version="14.0"
+   enabled="1"
+   name="transceiver_phy_inst"
+   autoexport="1">
+  <parameter name="device_family" value="Arria 10" />
+  <parameter name="device" value="10AX115R2F40I2LG" />
+  <parameter name="design_environment" value="NATIVE" />
+  <parameter name="message_level" value="error" />
+  <parameter name="support_mode" value="user_mode" />
+  <parameter name="protocol_mode" value="teng_baser_mode" />
+  <parameter name="pma_mode" value="basic" />
+  <parameter name="duplex_mode" value="duplex" />
+  <parameter name="channels" value="1" />
+  <parameter name="set_data_rate" value="10312.5" />
+  <parameter name="rcfg_iface_enable" value="0" />
+  <parameter name="enable_simple_interface" value="1" />
+  <parameter name="enable_split_interface" value="0" />
+  <parameter name="set_enable_calibration" value="0" />
+  <parameter name="enable_transparent_pcs" value="0" />
+  <parameter name="enable_parallel_loopback" value="0" />
+  <parameter name="bonded_mode" value="not_bonded" />
+  <parameter name="set_pcs_bonding_master" value="Auto" />
+  <parameter name="tx_pma_clk_div" value="1" />
+  <parameter name="plls" value="1" />
+  <parameter name="pll_select" value="0" />
+  <parameter name="enable_port_tx_pma_clkout" value="1" />
+  <parameter name="enable_port_tx_pma_div_clkout" value="1" />
+  <parameter name="tx_pma_div_clkout_divider" value="33" />
+  <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
+  <parameter name="enable_port_tx_pma_elecidle" value="0" />
+  <parameter name="enable_port_tx_pma_qpipullup" value="0" />
+  <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
+  <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
+  <parameter name="enable_port_tx_pma_rxfound" value="0" />
+  <parameter name="enable_port_rx_seriallpbken_tx" value="0" />
+  <parameter name="cdr_refclk_cnt" value="1" />
+  <parameter name="cdr_refclk_select" value="0" />
+  <parameter name="set_cdr_refclk_freq" value="644.531250" />
+  <parameter name="rx_ppm_detect_threshold" value="100" />
+  <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
+  <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
+  <parameter name="rx_pma_dfe_fixed_taps" value="3" />
+  <parameter name="enable_rx_pma_floatingtap" value="0" />
+  <parameter name="enable_ports_adaptation" value="0" />
+  <parameter name="enable_port_rx_pma_clkout" value="0" />
+  <parameter name="enable_port_rx_pma_div_clkout" value="0" />
+  <parameter name="rx_pma_div_clkout_divider" value="66" />
+  <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
+  <parameter name="enable_port_rx_pma_clkslip" value="0" />
+  <parameter name="enable_port_rx_pma_qpipullup" value="0" />
+  <parameter name="enable_port_rx_is_lockedtodata" value="1" />
+  <parameter name="enable_port_rx_is_lockedtoref" value="0" />
+  <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
+  <parameter name="enable_ports_rx_manual_ppm" value="0" />
+  <parameter name="enable_port_rx_signaldetect" value="0" />
+  <parameter name="enable_port_rx_seriallpbken" value="0" />
+  <parameter name="enable_ports_rx_prbs" value="0" />
+  <parameter name="std_pcs_pma_width" value="10" />
+  <parameter name="std_low_latency_bypass_enable" value="0" />
+  <parameter name="enable_hip" value="0" />
+  <parameter name="enable_hard_reset" value="0" />
+  <parameter name="set_hip_cal_en" value="0" />
+  <parameter name="std_tx_pcfifo_mode" value="low_latency" />
+  <parameter name="std_rx_pcfifo_mode" value="low_latency" />
+  <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
+  <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
+  <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
+  <parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
+  <parameter name="std_tx_byte_ser_mode" value="Disabled" />
+  <parameter name="std_rx_byte_deser_mode" value="Disabled" />
+  <parameter name="std_tx_8b10b_enable" value="1" />
+  <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
+  <parameter name="std_rx_8b10b_enable" value="1" />
+  <parameter name="std_rx_rmfifo_mode" value="disabled" />
+  <parameter name="std_rx_rmfifo_pattern_n" value="0" />
+  <parameter name="std_rx_rmfifo_pattern_p" value="0" />
+  <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+  <parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
+  <parameter name="pcie_rate_match" value="Bypass" />
+  <parameter name="std_tx_bitslip_enable" value="0" />
+  <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
+  <parameter name="std_rx_word_aligner_mode">synchronous state machine</parameter>
+  <parameter name="std_rx_word_aligner_pattern_len" value="7" />
+  <parameter name="std_rx_word_aligner_pattern" value="124" />
+  <parameter name="std_rx_word_aligner_rknumber" value="3" />
+  <parameter name="std_rx_word_aligner_renumber" value="3" />
+  <parameter name="std_rx_word_aligner_rgnumber" value="3" />
+  <parameter name="std_rx_word_aligner_rvnumber" value="0" />
+  <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
+  <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+  <parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
+  <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
+  <parameter name="enable_port_rx_std_bitslip" value="0" />
+  <parameter name="std_tx_bitrev_enable" value="0" />
+  <parameter name="std_tx_byterev_enable" value="0" />
+  <parameter name="std_tx_polinv_enable" value="0" />
+  <parameter name="enable_port_tx_polinv" value="0" />
+  <parameter name="std_rx_bitrev_enable" value="0" />
+  <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
+  <parameter name="std_rx_byterev_enable" value="0" />
+  <parameter name="enable_port_rx_std_byterev_ena" value="0" />
+  <parameter name="std_rx_polinv_enable" value="0" />
+  <parameter name="enable_port_rx_polinv" value="0" />
+  <parameter name="enable_port_rx_std_signaldetect" value="0" />
+  <parameter name="enable_ports_pipe_sw" value="0" />
+  <parameter name="enable_ports_pipe_hclk" value="0" />
+  <parameter name="enable_ports_pipe_g3_analog" value="0" />
+  <parameter name="enable_ports_pipe_rx_elecidle" value="0" />
+  <parameter name="enable_port_pipe_rx_polarity" value="0" />
+  <parameter name="enh_pcs_pma_width" value="32" />
+  <parameter name="enh_pld_pcs_width" value="66" />
+  <parameter name="enh_low_latency_enable" value="0" />
+  <parameter name="enh_rxtxfifo_double_width" value="0" />
+  <parameter name="enh_txfifo_mode" value="Phase compensation" />
+  <parameter name="enh_txfifo_pfull" value="11" />
+  <parameter name="enh_txfifo_pempty" value="2" />
+  <parameter name="enable_port_tx_enh_fifo_full" value="0" />
+  <parameter name="enable_port_tx_enh_fifo_pfull" value="0" />
+  <parameter name="enable_port_tx_enh_fifo_empty" value="0" />
+  <parameter name="enable_port_tx_enh_fifo_pempty" value="0" />
+  <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
+  <parameter name="enh_rxfifo_mode" value="10GBase-R" />
+  <parameter name="enh_rxfifo_pfull" value="23" />
+  <parameter name="enh_rxfifo_pempty" value="2" />
+  <parameter name="enh_rxfifo_align_del" value="0" />
+  <parameter name="enh_rxfifo_control_del" value="0" />
+  <parameter name="enable_port_rx_enh_data_valid" value="1" />
+  <parameter name="enable_port_rx_enh_fifo_full" value="0" />
+  <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
+  <parameter name="enable_port_rx_enh_fifo_empty" value="0" />
+  <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
+  <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
+  <parameter name="enable_port_rx_enh_fifo_del" value="0" />
+  <parameter name="enable_port_rx_enh_fifo_insert" value="0" />
+  <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
+  <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
+  <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
+  <parameter name="enh_tx_frmgen_enable" value="0" />
+  <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
+  <parameter name="enh_tx_frmgen_burst_enable" value="0" />
+  <parameter name="enable_port_tx_enh_frame" value="0" />
+  <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
+  <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
+  <parameter name="enh_rx_frmsync_enable" value="0" />
+  <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
+  <parameter name="enable_port_rx_enh_frame" value="0" />
+  <parameter name="enable_port_rx_enh_frame_lock" value="0" />
+  <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
+  <parameter name="enh_tx_crcgen_enable" value="0" />
+  <parameter name="enh_tx_crcerr_enable" value="0" />
+  <parameter name="enh_rx_crcchk_enable" value="0" />
+  <parameter name="enable_port_rx_enh_crc32_err" value="0" />
+  <parameter name="enable_port_rx_enh_highber" value="0" />
+  <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
+  <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
+  <parameter name="enh_tx_64b66b_enable" value="1" />
+  <parameter name="enh_rx_64b66b_enable" value="1" />
+  <parameter name="enh_tx_sh_err" value="0" />
+  <parameter name="enh_tx_scram_enable" value="1" />
+  <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+  <parameter name="enh_rx_descram_enable" value="1" />
+  <parameter name="enh_tx_dispgen_enable" value="0" />
+  <parameter name="enh_rx_dispchk_enable" value="0" />
+  <parameter name="enh_rx_blksync_enable" value="1" />
+  <parameter name="enable_port_rx_enh_blk_lock" value="1" />
+  <parameter name="enh_tx_bitslip_enable" value="0" />
+  <parameter name="enh_tx_polinv_enable" value="0" />
+  <parameter name="enh_rx_bitslip_enable" value="0" />
+  <parameter name="enh_rx_polinv_enable" value="0" />
+  <parameter name="enable_port_tx_enh_bitslip" value="0" />
+  <parameter name="enable_port_rx_enh_bitslip" value="0" />
+  <parameter name="enh_rx_krfec_err_mark_enable" value="0" />
+  <parameter name="enh_rx_krfec_err_mark_type" value="10G" />
+  <parameter name="enh_tx_krfec_burst_err_enable" value="0" />
+  <parameter name="enh_tx_krfec_burst_err_len" value="1" />
+  <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
+  <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
+  <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
+  <parameter name="pcs_direct_width" value="8" />
+  <parameter name="generate_docs" value="1" />
+  <parameter name="generate_add_hdl_instance_example" value="0" />
+  <parameter name="validation_rule_select" value="" />
+  <parameter name="rcfg_enable" value="0" />
+  <parameter name="rcfg_shared" value="0" />
+  <parameter name="rcfg_jtag_enable" value="0" />
+  <parameter name="set_embedded_debug_enable" value="0" />
+  <parameter name="set_capability_reg_enable" value="0" />
+  <parameter name="set_user_identifier" value="0" />
+  <parameter name="set_csr_soft_logic_enable" value="0" />
+  <parameter name="set_prbs_soft_logic_enable" value="0" />
+  <parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
+  <parameter name="rcfg_sv_file_enable" value="0" />
+  <parameter name="rcfg_h_file_enable" value="0" />
+  <parameter name="rcfg_mif_file_enable" value="0" />
+  <parameter name="rcfg_multi_enable" value="0" />
+  <parameter name="rcfg_reduced_files_enable" value="0" />
+  <parameter name="rcfg_profile_cnt" value="2" />
+  <parameter name="rcfg_profile_select" value="1" />
+  <parameter name="rcfg_profile_data0" value="" />
+  <parameter name="rcfg_profile_data1" value="" />
+  <parameter name="rcfg_profile_data2" value="" />
+  <parameter name="rcfg_profile_data3" value="" />
+  <parameter name="rcfg_profile_data4" value="" />
+  <parameter name="rcfg_profile_data5" value="" />
+  <parameter name="rcfg_profile_data6" value="" />
+  <parameter name="rcfg_profile_data7" value="" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+</system>