Moved the inferred IP to dedicated files for clarity.

libraries/technology/ip_arria10/ram/hdllib.cfg

@@ -7,6 +7,10 @@ build_dir_sim = $HDL_BUILD_DIR
 build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
+    ip_arria10_true_dual_port_ram_dual_clock.vhd
+    ip_arria10_simple_dual_port_ram_dual_clock.vhd
+    ip_arria10_simple_dual_port_ram_single_clock.vhd
+    
     ip_arria10_ram_crwk_crw.vhd
     ip_arria10_ram_crw_crw.vhd
     ip_arria10_ram_cr_cw.vhd

libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd

@@ -19,68 +19,6 @@
 --
 -------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
--- The inferred Altera code was obtained using template insert with Quartus 14.0a10.
-
--- Quartus II VHDL Template
--- Simple Dual-Port RAM with different read/write addresses and
--- different read/write clock
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity simple_dual_port_ram_dual_clock is
-
-  generic 
-  (
-    DATA_WIDTH : natural := 8;
-    ADDR_WIDTH : natural := 6
-  );
-
-  port 
-  (
-    rclk  : in std_logic;
-    wclk  : in std_logic;
-    raddr : in natural range 0 to 2**ADDR_WIDTH - 1;
-    waddr : in natural range 0 to 2**ADDR_WIDTH - 1;
-    data  : in std_logic_vector((DATA_WIDTH-1) downto 0);
-    we    : in std_logic := '1';
-    q   : out std_logic_vector((DATA_WIDTH -1) downto 0)
-  );
-
-end simple_dual_port_ram_dual_clock;
-
-architecture rtl of simple_dual_port_ram_dual_clock is
-
-  -- Build a 2-D array type for the RAM
-  subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
-  type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
-
-  -- Declare the RAM signal.  
-  signal ram : memory_t;
-
-begin
-
-  process(wclk)
-  begin
-  if(rising_edge(wclk)) then 
-    if(we = '1') then
-      ram(waddr) <= data;
-    end if;
-  end if;
-  end process;
-
-  process(rclk)
-  begin
-  if(rising_edge(rclk)) then 
-    q <= ram(raddr);
-  end if;
-  end process;
-
-end rtl;
-
-
--------------------------------------------------------------------------------
 -- RadioHDL wrapper
 
 LIBRARY ieee, technology_lib;
@@ -199,21 +137,21 @@ BEGIN
     rdaddr <= TO_INTEGER(UNSIGNED(rdaddress));
     wraddr <= TO_INTEGER(UNSIGNED(wraddress));
     
-    u_mem : entity work.simple_dual_port_ram_dual_clock
-    generic map (
-      DATA_WIDTH => g_dat_w,
-      ADDR_WIDTH => g_adr_w
-    )
-    port map (
-      rclk  => rdclk,
-      wclk  => wrclk,
-      raddr => rdaddr,
-      waddr => wraddr,
-      data  => data,
-      we    => wren,
-      q     => out_q
-    );
-  
+--    u_mem : entity work.ip_arria10_simple_dual_port_ram_dual_clock
+--    generic map (
+--      DATA_WIDTH => g_dat_w,
+--      ADDR_WIDTH => g_adr_w
+--    )
+--    port map (
+--      rclk  => rdclk,
+--      wclk  => wrclk,
+--      raddr => rdaddr,
+--      waddr => wraddr,
+--      data  => data,
+--      we    => wren,
+--      q     => out_q
+--    );
+--  
     reg_q <= out_q WHEN rising_edge(rdclk);
     
     q <= out_q WHEN g_rd_latency=1 ELSE reg_q;  

libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd

@@ -19,79 +19,6 @@
 --
 -------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
--- The inferred Altera code was obtained using template insert with Quartus 14.0a10.
-
--- Quartus II VHDL Template
--- True Dual-Port RAM with dual clock
---
--- Read-during-write on port A or B returns newly written data
--- 
--- Read-during-write on port A and B returns unknown data.
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity true_dual_port_ram_dual_clock is
-
-  generic 
-  (
-    DATA_WIDTH : natural := 8;
-    ADDR_WIDTH : natural := 6
-  );
-
-  port 
-  (
-    clk_a : in std_logic;
-    clk_b : in std_logic;
-    addr_a  : in natural range 0 to 2**ADDR_WIDTH - 1;
-    addr_b  : in natural range 0 to 2**ADDR_WIDTH - 1;
-    data_a  : in std_logic_vector((DATA_WIDTH-1) downto 0);
-    data_b  : in std_logic_vector((DATA_WIDTH-1) downto 0);
-    we_a  : in std_logic := '1';
-    we_b  : in std_logic := '1';
-    q_a   : out std_logic_vector((DATA_WIDTH -1) downto 0);
-    q_b   : out std_logic_vector((DATA_WIDTH -1) downto 0)
-  );
-
-end true_dual_port_ram_dual_clock;
-
-architecture rtl of true_dual_port_ram_dual_clock is
-
-  -- Build a 2-D array type for the RAM
-  subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
-  type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
-
-  -- Declare the RAM 
-  shared variable ram : memory_t;
-
-begin
-
-  -- Port A
-  process(clk_a)
-  begin
-  if(rising_edge(clk_a)) then 
-    if(we_a = '1') then
-      ram(addr_a) := data_a;
-    end if;
-    q_a <= ram(addr_a);
-  end if;
-  end process;
-
-  -- Port B
-  process(clk_b)
-  begin
-  if(rising_edge(clk_b)) then 
-    if(we_b = '1') then
-      ram(addr_b) := data_b;
-    end if;
-    q_b <= ram(addr_b);
-  end if;
-  end process;
-
-end rtl;
-
--------------------------------------------------------------------------------
 -- RadioHDL wrapper
 
 LIBRARY ieee, technology_lib;
@@ -235,7 +162,7 @@ BEGIN
     addr_a <= TO_INTEGER(UNSIGNED(address_a));
     addr_b <= TO_INTEGER(UNSIGNED(address_b));
   
-    u_mem : entity work.true_dual_port_ram_dual_clock
+    u_mem : entity work.ip_arria10_true_dual_port_ram_dual_clock
     generic map (
       DATA_WIDTH => g_dat_w,
       ADDR_WIDTH => g_adr_w

libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd

@@ -19,62 +19,6 @@
 --
 -------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
--- The inferred Altera code was obtained using template insert with Quartus 14.0a10.
--- Quartus II VHDL Template
--- Simple Dual-Port RAM with different read/write addresses but
--- single read/write clock
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity simple_dual_port_ram_single_clock is
-
-  generic 
-  (
-    DATA_WIDTH : natural := 8;
-    ADDR_WIDTH : natural := 6
-  );
-
-  port 
-  (
-    clk   : in std_logic;
-    raddr : in natural range 0 to 2**ADDR_WIDTH - 1;
-    waddr : in natural range 0 to 2**ADDR_WIDTH - 1;
-    data  : in std_logic_vector((DATA_WIDTH-1) downto 0);
-    we    : in std_logic := '1';
-    q   : out std_logic_vector((DATA_WIDTH -1) downto 0)
-  );
-
-end simple_dual_port_ram_single_clock;
-
-architecture rtl of simple_dual_port_ram_single_clock is
-
-  -- Build a 2-D array type for the RAM
-  subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
-  type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
-
-  -- Declare the RAM signal.  
-  signal ram : memory_t;
-
-begin
-
-  process(clk)
-  begin
-  if(rising_edge(clk)) then 
-    if(we = '1') then
-      ram(waddr) <= data;
-    end if;
- 
-    -- On a read during a write to the same address, the read will
-    -- return the OLD data at the address
-    q <= ram(raddr);
-  end if;
-  end process;
-
-end rtl;
-
--------------------------------------------------------------------------------
 -- RadioHDL wrapper
 
 LIBRARY ieee, technology_lib;
@@ -189,7 +133,7 @@ BEGIN
     rdaddr <= TO_INTEGER(UNSIGNED(rdaddress));
     wraddr <= TO_INTEGER(UNSIGNED(wraddress));
   
-    u_mem : entity work.simple_dual_port_ram_single_clock
+    u_mem : entity work.ip_arria10_simple_dual_port_ram_single_clock
     generic map (
       DATA_WIDTH => g_dat_w,
       ADDR_WIDTH => g_adr_w

libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_dual_clock.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- The inferred Altera code was obtained using template insert with Quartus 14.0a10.
+
+-- Quartus II VHDL Template
+-- Simple Dual-Port RAM with different read/write addresses and
+-- different read/write clock
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ip_arria10_simple_dual_port_ram_dual_clock is
+
+  generic 
+  (
+    DATA_WIDTH : natural := 8;
+    ADDR_WIDTH : natural := 6
+  );
+
+  port 
+  (
+    rclk  : in std_logic;
+    wclk  : in std_logic;
+    raddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+    waddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+    data  : in std_logic_vector((DATA_WIDTH-1) downto 0);
+    we    : in std_logic := '1';
+    q   : out std_logic_vector((DATA_WIDTH -1) downto 0)
+  );
+
+end ip_arria10_simple_dual_port_ram_dual_clock;
+
+architecture rtl of ip_arria10_simple_dual_port_ram_dual_clock is
+
+  -- Build a 2-D array type for the RAM
+  subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
+  type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
+
+  -- Declare the RAM signal.  
+  signal ram : memory_t;
+
+begin
+
+  process(wclk)
+  begin
+  if(rising_edge(wclk)) then 
+    if(we = '1') then
+      ram(waddr) <= data;
+    end if;
+  end if;
+  end process;
+
+  process(rclk)
+  begin
+  if(rising_edge(rclk)) then 
+    q <= ram(raddr);
+  end if;
+  end process;
+
+end rtl;

libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_single_clock.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- The inferred Altera code was obtained using template insert with Quartus 14.0a10.
+-- Quartus II VHDL Template
+-- Simple Dual-Port RAM with different read/write addresses but
+-- single read/write clock
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ip_arria10_simple_dual_port_ram_single_clock is
+
+  generic 
+  (
+    DATA_WIDTH : natural := 8;
+    ADDR_WIDTH : natural := 6
+  );
+
+  port 
+  (
+    clk   : in std_logic;
+    raddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+    waddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+    data  : in std_logic_vector((DATA_WIDTH-1) downto 0);
+    we    : in std_logic := '1';
+    q   : out std_logic_vector((DATA_WIDTH -1) downto 0)
+  );
+
+end ip_arria10_simple_dual_port_ram_single_clock;
+
+architecture rtl of ip_arria10_simple_dual_port_ram_single_clock is
+
+  -- Build a 2-D array type for the RAM
+  subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
+  type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
+
+  -- Declare the RAM signal.  
+  signal ram : memory_t;
+
+begin
+
+  process(clk)
+  begin
+  if(rising_edge(clk)) then 
+    if(we = '1') then
+      ram(waddr) <= data;
+    end if;
+ 
+    -- On a read during a write to the same address, the read will
+    -- return the OLD data at the address
+    q <= ram(raddr);
+  end if;
+  end process;
+
+end rtl;
+

libraries/technology/ip_arria10/ram/ip_arria10_true_dual_port_ram_dual_clock.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- The inferred Altera code was obtained using template insert with Quartus 14.0a10.
+
+-- Quartus II VHDL Template
+-- True Dual-Port RAM with dual clock
+--
+-- Read-during-write on port A or B returns newly written data
+-- 
+-- Read-during-write on port A and B returns unknown data.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ip_arria10_true_dual_port_ram_dual_clock is
+
+  generic 
+  (
+    DATA_WIDTH : natural := 8;
+    ADDR_WIDTH : natural := 6
+  );
+
+  port 
+  (
+    clk_a : in std_logic;
+    clk_b : in std_logic;
+    addr_a  : in natural range 0 to 2**ADDR_WIDTH - 1;
+    addr_b  : in natural range 0 to 2**ADDR_WIDTH - 1;
+    data_a  : in std_logic_vector((DATA_WIDTH-1) downto 0);
+    data_b  : in std_logic_vector((DATA_WIDTH-1) downto 0);
+    we_a  : in std_logic := '1';
+    we_b  : in std_logic := '1';
+    q_a   : out std_logic_vector((DATA_WIDTH -1) downto 0);
+    q_b   : out std_logic_vector((DATA_WIDTH -1) downto 0)
+  );
+
+end ip_arria10_true_dual_port_ram_dual_clock;
+
+architecture rtl of ip_arria10_true_dual_port_ram_dual_clock is
+
+  -- Build a 2-D array type for the RAM
+  subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
+  type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
+
+  -- Declare the RAM 
+  shared variable ram : memory_t;
+
+begin
+
+  -- Port A
+  process(clk_a)
+  begin
+  if(rising_edge(clk_a)) then 
+    if(we_a = '1') then
+      ram(addr_a) := data_a;
+    end if;
+    q_a <= ram(addr_a);
+  end if;
+  end process;
+
+  -- Port B
+  process(clk_b)
+  begin
+  if(rising_edge(clk_b)) then 
+    if(we_b = '1') then
+      ram(addr_b) := data_b;
+    end if;
+    q_b <= ram(addr_b);
+  end if;
+  end process;
+
+end rtl;