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Commit e1ae9d7b authored by Daniel van der Schuur's avatar Daniel van der Schuur
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-Added block gens, correlator and data buffers.

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applications/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
+ 97
− 10
View file @ e1ae9d7b
......@@ -64,6 +64,12 @@ ENTITY mmm_unb1_correlator IS
reg_ppsh_mosi : OUT t_mem_mosi;
reg_ppsh_miso : IN t_mem_miso;
-- Data buffers
reg_diag_data_buf_mosi : OUT t_mem_mosi;
reg_diag_data_buf_miso : IN t_mem_miso;
ram_diag_data_buf_mosi : OUT t_mem_mosi;
ram_diag_data_buf_miso : IN t_mem_miso;
-- eth1g
eth1g_tse_clk : OUT STD_LOGIC;
eth1g_mm_rst : OUT STD_LOGIC;
......@@ -107,8 +113,76 @@ ARCHITECTURE str OF mmm_unb1_correlator IS
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
-----------------------------------------------------------------------------
COMPONENT qsys_unb1_correlator is
PORT (
-- COMPONENT qsys_unb1_correlator is
-- PORT (
-- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
-- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
-- mm_clk : out std_logic; -- clk
-- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
-- coe_address_export_from_the_pio_pps : out std_logic;--_vector(0 downto 0); -- export
-- coe_reset_export_from_the_pio_pps : out std_logic; -- export
-- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
-- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
-- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
-- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
-- coe_reset_export_from_the_reg_wdi : out std_logic; -- export
-- coe_clk_export_from_the_rom_system_info : out std_logic; -- export
-- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
-- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
-- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
-- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
-- coe_read_export_from_the_reg_wdi : out std_logic; -- export
-- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
-- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
-- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
-- coe_clk_export_from_the_pio_pps : out std_logic; -- export
-- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
-- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
-- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
-- coe_address_export_from_the_reg_wdi : out std_logic;--_vector(0 downto 0); -- export
-- coe_write_export_from_the_pio_system_info : out std_logic; -- export
-- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
-- coe_write_export_from_the_pio_pps : out std_logic; -- export
-- coe_write_export_from_the_rom_system_info : out std_logic; -- export
-- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
-- phasedone_from_the_altpll_0 : out std_logic; -- export
-- coe_read_export_from_the_rom_system_info : out std_logic; -- export
-- reset_n : in std_logic := 'X'; -- reset_n
-- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
-- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
-- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
-- clk_0 : in std_logic := 'X'; -- clk
-- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
-- tse_clk : out std_logic; -- clk
-- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
-- epcs_clk : out std_logic; -- clk
-- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
-- out_port_from_the_pio_debug_wave : out std_logic_vector(31 downto 0); -- export
-- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
-- coe_reset_export_from_the_pio_system_info : out std_logic; -- export
-- coe_read_export_from_the_pio_system_info : out std_logic; -- export
-- coe_clk_export_from_the_reg_wdi : out std_logic; -- export
-- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
-- out_port_from_the_pio_wdi : out std_logic; -- export
-- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
-- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
-- coe_write_export_from_the_reg_wdi : out std_logic; -- export
-- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
-- coe_read_export_from_the_pio_pps : out std_logic; -- export
-- coe_clk_export_from_the_pio_system_info : out std_logic; -- export
-- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
-- coe_reset_export_from_the_rom_system_info : out std_logic; -- export
-- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
-- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
-- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
-- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
-- areset_to_the_altpll_0 : in std_logic := 'X'; -- export
-- locked_from_the_altpll_0 : out std_logic; -- export
-- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0) -- export
-- );
-- end component qsys_unb1_correlator;
component qsys_unb1_correlator is
port (
coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
mm_clk : out std_logic; -- clk
......@@ -132,26 +206,26 @@ ARCHITECTURE str OF mmm_unb1_correlator IS
coe_clk_export_from_the_pio_pps : out std_logic; -- export
coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
coe_address_export_from_the_reg_wdi : out std_logic;--_vector(0 downto 0); -- export
coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
coe_write_export_from_the_pio_system_info : out std_logic; -- export
coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
coe_write_export_from_the_pio_pps : out std_logic; -- export
coe_write_export_from_the_rom_system_info : out std_logic; -- export
coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
phasedone_from_the_altpll_0 : out std_logic; -- export
coe_read_export_from_the_rom_system_info : out std_logic; -- export
phasedone_from_the_altpll_0 : out std_logic; -- export
reset_n : in std_logic := 'X'; -- reset_n
coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
clk_0 : in std_logic := 'X'; -- clk
coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
tse_clk : out std_logic; -- clk
coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
epcs_clk : out std_logic; -- clk
coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
out_port_from_the_pio_debug_wave : out std_logic_vector(31 downto 0); -- export
coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
coe_reset_export_from_the_pio_system_info : out std_logic; -- export
coe_read_export_from_the_pio_system_info : out std_logic; -- export
......@@ -168,14 +242,27 @@ ARCHITECTURE str OF mmm_unb1_correlator IS
coe_reset_export_from_the_rom_system_info : out std_logic; -- export
coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
areset_to_the_altpll_0 : in std_logic := 'X'; -- export
locked_from_the_altpll_0 : out std_logic; -- export
coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0) -- export
coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
c3_from_the_altpll_0 : out std_logic; -- export
ram_diag_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
ram_diag_data_buf_read_export : out std_logic; -- export
ram_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_diag_data_buf_write_export : out std_logic; -- export
ram_diag_data_buf_address_export : out std_logic_vector(16 downto 0); -- export
ram_diag_data_buf_clk_export : out std_logic; -- export
ram_diag_data_buf_reset_export : out std_logic; -- export
reg_diag_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_data_buf_read_export : out std_logic; -- export
reg_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_data_buf_write_export : out std_logic; -- export
reg_diag_data_buf_address_export : out std_logic_vector(9 downto 0); -- export
reg_diag_data_buf_clk_export : out std_logic -- export
);
end component qsys_unb1_correlator;
BEGIN
mm_clk <= i_mm_clk;
......
applications/unb1_correlator/src/vhdl/unb1_correlator.vhd
+ 103
− 6
View file @ e1ae9d7b
......@@ -20,12 +20,14 @@
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb1_board_lib;
LIBRARY IEEE, common_lib, unb1_board_lib, correlator_lib, diag_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
ENTITY unb1_correlator IS
GENERIC (
......@@ -113,8 +115,100 @@ ARCHITECTURE str OF unb1_correlator IS
SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
SIGNAL eth1g_ram_miso : t_mem_miso;
-- Correlator
CONSTANT c_nof_inputs : NATURAL := 24;
CONSTANT c_nof_mults : NATURAL := (c_nof_inputs*(c_nof_inputs+1))/2;
CONSTANT c_data_w : NATURAL := 32;
-- Block generator
CONSTANT c_bg_block_size : NATURAL := 1024;
CONSTANT c_bg_gapsize : NATURAL := 0;
CONSTANT c_bg_blocks_per_sync : NATURAL := 10;
CONSTANT c_bg_ctrl : t_diag_block_gen := ('1', -- enable
'0', -- enable_sync
TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
TO_UVEC( 0, c_diag_bg_bsn_init_w));
SIGNAL correlator_snk_in_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
SIGNAL correlator_src_out_arr : t_dp_sosi_arr(c_nof_inputs*(c_nof_inputs+1)/2-1 DOWNTO 0);
SIGNAL ram_diag_data_buf_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_miso : t_mem_miso;
BEGIN
-----------------------------------------------------------------------------
-- Block generators
-- . Each stream in block_gen_src_out_arr contains complex subband samples
-- from one 'antenna'.
-- . These complex subband samples are generated and converted to a HEX RAM
-- initialization file using Python, see tb/python/gen_subband_hex_files.py
-----------------------------------------------------------------------------
u_mms_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen
GENERIC MAP (
g_nof_output_streams => c_nof_inputs,
g_buf_dat_w => c_data_w,
g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
g_file_name_prefix => "../../../libraries/dsp/correlator/src/hex/complex_subbands_" & NATURAL'IMAGE(c_data_w/2),
g_diag_block_gen_rst => c_bg_ctrl
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
out_sosi_arr => correlator_snk_in_arr
);
-----------------------------------------------------------------------------
-- Correlator
-----------------------------------------------------------------------------
u_correlator : ENTITY correlator_lib.correlator
GENERIC MAP (
g_nof_inputs => c_nof_inputs,
g_nof_mults => c_nof_mults
)
PORT MAP (
clk => dp_clk,
rst => dp_rst,
snk_in_arr => correlator_snk_in_arr,
src_out_arr => correlator_src_out_arr
);
-----------------------------------------------------------------------------
-- Data buffers to be read out by Python
-----------------------------------------------------------------------------
u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
g_nof_streams => c_nof_mults,
g_data_w => c_data_w,
g_data_type => e_complex,
g_buf_nof_data => 256, --c_bg_block_size,
g_buf_use_sync => FALSE
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
ram_data_buf_mosi => ram_diag_data_buf_mosi,
ram_data_buf_miso => ram_diag_data_buf_miso,
reg_data_buf_mosi => reg_diag_data_buf_mosi,
reg_data_buf_miso => reg_diag_data_buf_miso,
in_sosi_arr => correlator_src_out_arr
);
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
......@@ -152,10 +246,6 @@ BEGIN
-- Toggle WDI
pout_wdi => pout_wdi,
-- REMU
reg_remu_mosi => reg_remu_mosi,
reg_remu_miso => reg_remu_miso,
-- MM buses
-- . Manual WDI override
reg_wdi_mosi => reg_wdi_mosi,
......@@ -245,6 +335,13 @@ BEGIN
reg_ppsh_mosi => reg_ppsh_mosi,
reg_ppsh_miso => reg_ppsh_miso,
-- . Data buffers
reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
reg_diag_data_buf_miso => reg_diag_data_buf_miso,
ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
ram_diag_data_buf_miso => ram_diag_data_buf_miso,
-- eth1g
eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
......
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