pll to drive 156.25 and 312.5 MHz clocks for xgmii and mac

libraries/technology/ip_arria10/transceiver_phy_48/transceiver_phy_48.qsys

@@ -23,7 +23,7 @@
 }
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2SGES" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
  <parameter name="deviceFamily" value="Arria 10" />
  <parameter name="deviceSpeedGrade" value="2" />
  <parameter name="fabricMode" value="QSYS" />
@@ -229,6 +229,34 @@
    dir="end">
   <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
  </interface>
+ <interface
+   name="tx_pma_div_clkout"
+   internal="transceiver_phy_inst.tx_pma_div_clkout"
+   type="conduit"
+   dir="end">
+  <port name="tx_pma_div_clkout" internal="tx_pma_div_clkout" />
+ </interface>
+ <interface
+   name="tx_pma_clkout"
+   internal="transceiver_phy_inst.tx_pma_clkout"
+   type="conduit"
+   dir="end">
+  <port name="tx_pma_clkout" internal="tx_pma_clkout" />
+ </interface>
+ <interface
+   name="rx_pma_clkout"
+   internal="transceiver_phy_inst.rx_pma_clkout"
+   type="conduit"
+   dir="end">
+  <port name="rx_pma_clkout" internal="rx_pma_clkout" />
+ </interface>
+ <interface
+   name="rx_pma_div_clkout"
+   internal="transceiver_phy_inst.rx_pma_div_clkout"
+   type="conduit"
+   dir="end">
+  <port name="rx_pma_div_clkout" internal="rx_pma_div_clkout" />
+ </interface>
  <module
    kind="altera_xcvr_native_a10"
    version="14.0"
@@ -236,7 +264,7 @@
    name="transceiver_phy_inst"
    autoexport="1">
   <parameter name="device_family" value="Arria 10" />
-  <parameter name="device" value="10AX115U3F45I2SGES" />
+  <parameter name="device" value="10AX115U3F45I2LG" />
   <parameter name="design_environment" value="NATIVE" />
   <parameter name="message_level" value="error" />
   <parameter name="support_mode" value="user_mode" />
@@ -256,9 +284,9 @@
   <parameter name="tx_pma_clk_div" value="1" />
   <parameter name="plls" value="1" />
   <parameter name="pll_select" value="0" />
-  <parameter name="enable_port_tx_pma_clkout" value="0" />
-  <parameter name="enable_port_tx_pma_div_clkout" value="0" />
-  <parameter name="tx_pma_div_clkout_divider" value="33" />
+  <parameter name="enable_port_tx_pma_clkout" value="1" />
+  <parameter name="enable_port_tx_pma_div_clkout" value="1" />
+  <parameter name="tx_pma_div_clkout_divider" value="66" />
   <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
   <parameter name="enable_port_tx_pma_elecidle" value="0" />
   <parameter name="enable_port_tx_pma_qpipullup" value="0" />
@@ -275,9 +303,9 @@
   <parameter name="rx_pma_dfe_fixed_taps" value="3" />
   <parameter name="enable_rx_pma_floatingtap" value="0" />
   <parameter name="enable_ports_adaptation" value="0" />
-  <parameter name="enable_port_rx_pma_clkout" value="0" />
-  <parameter name="enable_port_rx_pma_div_clkout" value="0" />
-  <parameter name="rx_pma_div_clkout_divider" value="0" />
+  <parameter name="enable_port_rx_pma_clkout" value="1" />
+  <parameter name="enable_port_rx_pma_div_clkout" value="1" />
+  <parameter name="rx_pma_div_clkout_divider" value="66" />
   <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
   <parameter name="enable_port_rx_pma_clkslip" value="0" />
   <parameter name="enable_port_rx_pma_qpipullup" value="0" />