add pll to generate 156 and 312MHz clocks

libraries/technology/transceiver/tech_transceiver_arria10_48.vhd

@@ -34,6 +34,8 @@ entity tech_transceiver_arria10_48 is
       clk                     : in  std_logic;
       reset_p                 : in  std_logic;
       refclk                  : in  std_logic;
+      clk_156_arr             : out std_logic_vector(g_nof_channels-1 downto 0);
+      clk_312_arr             : out std_logic_vector(g_nof_channels-1 downto 0);
       tx_serial_data          : out std_logic_vector(g_nof_channels-1 downto 0);  
       rx_serial_data          : in  std_logic_vector(g_nof_channels-1 downto 0);
       tx_parallel_data        : in  std_logic_vector(64*g_nof_channels-1 downto 0);    
@@ -63,6 +65,10 @@ architecture str of tech_transceiver_arria10_48 is
       rx_coreclkin            : in  std_logic_vector(47 downto 0)   := (others => 'X'); -- clk
       tx_clkout               : out std_logic_vector(47 downto 0);                      -- clk
       rx_clkout               : out std_logic_vector(47 downto 0);                      -- clk
+      tx_pma_clkout           : out std_logic_vector(47 downto 0);                      -- clk
+      tx_pma_div_clkout       : out std_logic_vector(47 downto 0);                      -- clk
+      rx_pma_clkout           : out std_logic_vector(47 downto 0);                      -- clk
+      rx_pma_div_clkout       : out std_logic_vector(47 downto 0);                      -- clk
       tx_enh_data_valid       : in  std_logic_vector(47 downto 0)   := (others => 'X'); -- tx_enh_data_valid
       rx_enh_data_valid       : out std_logic_vector(47 downto 0);                      -- rx_enh_data_valid
       rx_enh_blk_lock         : out std_logic_vector(47 downto 0);                      -- rx_enh_blk_lock
@@ -108,9 +114,21 @@ architecture str of tech_transceiver_arria10_48 is
     );
   end component transceiver_pll;
 
+  component pll_xgmii_mac_clocks is
+    port (
+      pll_refclk0     : in  std_logic := 'X'; -- clk
+      pll_powerdown   : in  std_logic := 'X'; -- pll_powerdown
+      pll_locked      : out std_logic;        -- pll_locked
+      outclk0         : out std_logic;        -- clk
+      pll_cal_busy    : out std_logic;        -- pll_cal_busy
+      outclk1         : out std_logic         -- clk
+    );
+  end component pll_xgmii_mac_clocks;
+
   -- signals for the transceivers
   signal tx_data_valid     : std_logic_vector(g_nof_channels-1 downto 0) := (others => '1');
-  signal tx_serdesclk      : std_logic_vector(g_nof_channels-1 downto 0);
+  signal tx_clk            : std_logic_vector(g_nof_channels-1 downto 0);
+  signal rx_clk            : std_logic_vector(g_nof_channels-1 downto 0);
   signal tx_analogreset    : std_logic_vector(g_nof_channels-1 downto 0);
   signal tx_digitalreset   : std_logic_vector(g_nof_channels-1 downto 0);
   signal rx_analogreset    : std_logic_vector(g_nof_channels-1 downto 0);
@@ -125,9 +143,18 @@ architecture str of tech_transceiver_arria10_48 is
   signal tx_serial_clk     : std_logic_vector(g_nof_channels-1 downto 0);
   signal mcgb_serial_clk   : std_logic;
 
+  signal tx_pma_clkout     : std_logic_vector(g_nof_channels-1 downto 0);
+  signal tx_pma_div_clkout : std_logic_vector(g_nof_channels-1 downto 0);
+  signal rx_pma_clkout     : std_logic_vector(g_nof_channels-1 downto 0);
+  signal rx_pma_div_clkout : std_logic_vector(g_nof_channels-1 downto 0);
+  signal clk_156_internal  : std_logic_vector(g_nof_channels-1 downto 0);
+  signal clk_312_internal  : std_logic_vector(g_nof_channels-1 downto 0);
+  signal clk_156           : std_logic;
+  signal clk_312           : std_logic;
 
 begin
 
+
   transceiver_phy : transceiver_phy_48
     port map (
       tx_analogreset          => tx_analogreset,
@@ -141,10 +168,14 @@ begin
       rx_cdr_refclk0          => refclk,
       tx_serial_data          => tx_serial_data,
       rx_serial_data          => rx_serial_data,
-      tx_coreclkin            => tx_serdesclk, -- write side clock for tx fifo
-      rx_coreclkin            => tx_serdesclk,
-      tx_clkout               => tx_serdesclk, 
-      rx_clkout               => open,
+      tx_coreclkin            => clk_156_internal, -- write side clock for tx fifo
+      rx_coreclkin            => clk_156_internal,
+      tx_clkout               => tx_clk, 
+      rx_clkout               => rx_clk,
+      tx_pma_clkout           => tx_pma_clkout,
+      tx_pma_div_clkout       => tx_pma_div_clkout,
+      rx_pma_clkout           => rx_pma_clkout,
+      rx_pma_div_clkout       => rx_pma_div_clkout,
       tx_enh_data_valid       => tx_data_valid,
       rx_enh_data_valid       => open,
       rx_enh_blk_lock         => open,
@@ -190,4 +221,20 @@ begin
   tx_serial_clk <= (others => mcgb_serial_clk);
   txpll_cal_busy <= tx_cal_busy when pll_cal_busy = '0' else (others => '1');
 
+  u_pll_xgmii_mac_clocks : component pll_xgmii_mac_clocks
+    port map (
+      pll_refclk0   => refclk,   --   pll_refclk0.clk
+      pll_powerdown => reset_p, -- pll_powerdown.pll_powerdown
+      pll_locked    => open,    --    pll_locked.pll_locked
+      outclk0       => clk_156,       --       outclk0.clk
+      pll_cal_busy  => open,  --  pll_cal_busy.pll_cal_busy
+      outclk1       => clk_312        --       outclk1.clk
+   );
+
+  clk_156_internal <= (others => clk_156);
+  clk_312_internal <= (others => clk_312);
+  clk_156_arr      <= clk_156_internal;
+  clk_312_arr      <= clk_312_internal;
+
+
 end;