Use g_rd_fifo_af_margin to fit one (DDR3 IP) or more (DDR4 IP) rd burst accesses of g_tech_ddr.maxburstsize each.

Improved check on snk_diag_res by placing it after the read FIFO has been read empty. No need for using v_diag_first_rd to ensure that snk_diag_res_val has become 1.

Added to do plan for: hdltool.cfg per toolset, generate IP, only central build tree, location of modelsim_project_files.txt, support multiple  --technology.

Improved stimuli using generics and functions to define the write and read block accesses. Distinghuis between tests for DDR3 and DDR4, because DDR4 model simulates about 20x slower.

- Added io_ddr to the testbench after removing it from the DUT. 

-Updated port map to interface with external io_ddr

- Added tech generics
- Removed old ddr3 generics
- Updated porttypes
- replaced ddr3 by io_ddr