Removed internal DDR memory model (now needs to be instantiated in tb). Use dedicated records for DDR3 and DDR4 phy interfaces, instead of the combined record.

Removed g_use_ddr_memory_model so the DDR memory model code is not seen/needed by synthesis. Instead only support DDR memory model instantiation in test bench.

Improved check on snk_diag_res by placing it after the read FIFO has been read empty. No need for using v_diag_first_rd to ensure that snk_diag_res_val has become 1.

Added g_sim, when TRUE then use internal DDR memory model in tech_ddr component. When FALSE use DDR memory model in test bench.

Check UNSIGNED(wr_fifo_usedw) < c_dp_factor, because a mixed width FIFO cannot always be flushed completely empty, which is ok.diff

Added io_ddr_cross_domain.vhd to handle dvr_clk and ctlr_clk domains in case they are different clock domains.

Redefined write flush modes. Now the flush is still under control by dvr_flush_en, and disabled when kept tied to '0'.

Clarified clock domains and use ctlr_clk_out and ctlr_clk_in to make ctlr_clk available in same delta-cycle.

Instantiate tech_ddr_lib.tech_ddr_memory_model. Use dp_clk for rd and wr. DDR3 access starts but diagnostic result fails.diff

Ported $UNB ddr3.vhd to $RADIOHDL io_ddr.vhd. Initial version, still needs to be compiled and simulated with tb_io_ddr.vhd.