Commits · e50aab24a6fbb597291ce8b332bdb587faab8487 · RTSD / HDL

Feb 15, 2017
- Modify technology wrappers to include unb2b FPGA Arria 10 version e1sg · e50aab24
  Jonathan Hargreaves authored 8 years ago
  
  e50aab24
Mar 10, 2016
- add ddr4_8g_1600 to packages and wrappers · eecc4c7e
  Jonathan Hargreaves authored 9 years ago
  
  eecc4c7e
Jan 29, 2016
- update technology wrapper to include device e3sge3 for unb2a · 16efe183
  Jonathan Hargreaves authored 9 years ago
  
  16efe183
Oct 12, 2015
- Aligned interfaces · ffd65ec4
  Zanting authored 9 years ago
  
  ffd65ec4
Sep 30, 2015
- Reverted to own pll/dll for 4g single rank slave · cde216f4
  Zanting authored 9 years ago
  
  cde216f4
- IP for 16GB DDR3 So-Dimm modules added · 4750ad20
  Zanting authored 9 years ago
  
  4750ad20
Aug 18, 2015
- added ddr4_4g_2000 IP · 08d9a16e
  Kenneth Hiemstra authored 9 years ago
  
  08d9a16e
Apr 29, 2015
- Fixed connections to single rank memory · ade1b60b
  Zanting authored 10 years ago
  
  ade1b60b
Apr 22, 2015
- Added DDR3 single rank master and slave · 0b1592e6
  Zanting authored 10 years ago
  
  0b1592e6
Jan 20, 2015
- Added ip_arria10 DDR4 IP for 4Gbyte, 1600 MTps. · 0c910766
  Eric Kooistra authored 10 years ago
  
  0c910766
Dec 19, 2014
- No need for technology_lib. · da6b89d9
  Eric Kooistra authored 10 years ago
  
  da6b89d9
Dec 18, 2014
- Moved ddr3/ VHDL files to ddr/. · 6d479748
  Eric Kooistra authored 10 years ago
  
  6d479748
Dec 15, 2014
- Added dir technology/ddr3. · 7aa6520f
  Eric Kooistra authored 10 years ago
  
  7aa6520f