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Commit 7aa6520f authored by Eric Kooistra's avatar Eric Kooistra
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Added dir technology/ddr3.

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libraries/technology/ddr3/hdllib.cfg 0 → 100644
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View file @ 7aa6520f
hdl_lib_name = tech_ddr3
hdl_library_clause_name = tech_ddr3_lib
hdl_lib_uses = technology ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave
hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files =
tech_ddr3_component_pkg.vhd
#tech_ddr3_stratixiv.vhd
#tech_ddr3.vhd
test_bench_files =
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
libraries/technology/ddr3/tech_ddr3_component_pkg.vhd 0 → 100644
+ 143
− 0
View file @ 7aa6520f
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: IP components declarations for various devices that get wrapped by the tech components
LIBRARY IEEE, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE technology_lib.technology_pkg.ALL;
PACKAGE tech_ddr3_component_pkg IS
------------------------------------------------------------------------------
-- ip_stratixiv
------------------------------------------------------------------------------
-- Manually derived VHDL entity from Verilog module $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.v
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_master IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
global_reset_n : IN STD_LOGIC; -- global_reset.reset_n
soft_reset_n : IN STD_LOGIC; -- soft_reset.reset_n
afi_clk : OUT STD_LOGIC; -- afi_clk.clk
afi_half_clk : OUT STD_LOGIC; -- afi_half_clk.clk
afi_reset_n : OUT STD_LOGIC; -- afi_reset.reset_n
mem_a : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); -- memory.mem_a
mem_ba : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- .mem_ba
mem_ck : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck
mem_ck_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck_n
mem_cke : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_cke
mem_cs_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_cs_n
mem_dm : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dm
mem_ras_n : OUT STD_LOGIC; -- .mem_ras_n
mem_cas_n : OUT STD_LOGIC; -- .mem_cas_n
mem_we_n : OUT STD_LOGIC; -- .mem_we_n
mem_reset_n : OUT STD_LOGIC; -- .mem_reset_n
mem_dq : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- .mem_dq
mem_dqs : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs
mem_dqs_n : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs_n
mem_odt : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_odt
avl_ready : OUT STD_LOGIC; -- avl.waitrequest_n
avl_burstbegin : IN STD_LOGIC; -- .beginbursttransfer
avl_addr : IN STD_LOGIC_VECTOR(26 DOWNTO 0); -- .address
avl_rdata_valid : OUT STD_LOGIC; -- .readdatavalid
avl_rdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); -- .readdata
avl_wdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); -- .writedata
avl_be : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- .byteenable
avl_read_req : IN STD_LOGIC; -- .read
avl_write_req : IN STD_LOGIC; -- .write
avl_size : IN STD_LOGIC_VECTOR(6 DOWNTO 0); -- .burstcount
local_init_done : OUT STD_LOGIC; -- status.local_init_done
local_cal_success : OUT STD_LOGIC; -- .local_cal_success
local_cal_fail : OUT STD_LOGIC; -- .local_cal_fail
oct_rdn : IN STD_LOGIC; -- oct.rdn
oct_rup : IN STD_LOGIC; -- .rup
seriesterminationcontrol : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); -- oct_sharing.seriesterminationcontrol
parallelterminationcontrol : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); -- .parallelterminationcontrol
pll_mem_clk : OUT STD_LOGIC; -- pll_sharing.pll_mem_clk
pll_write_clk : OUT STD_LOGIC; -- .pll_write_clk
pll_write_clk_pre_phy_clk : OUT STD_LOGIC; -- .pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : OUT STD_LOGIC; -- .pll_addr_cmd_clk
pll_locked : OUT STD_LOGIC; -- .pll_locked
pll_avl_clk : OUT STD_LOGIC; -- .pll_avl_clk
pll_config_clk : OUT STD_LOGIC; -- .pll_config_clk
dll_delayctrl : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) -- dll_sharing.dll_delayctrl
);
END COMPONENT;
-- Manually derived VHDL entity from Verilog module $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.v
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_slave IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
global_reset_n : IN STD_LOGIC; -- global_reset.reset_n
soft_reset_n : IN STD_LOGIC; -- soft_reset.reset_n
afi_clk : OUT STD_LOGIC; -- afi_clk.clk
afi_half_clk : OUT STD_LOGIC; -- afi_half_clk.clk
afi_reset_n : OUT STD_LOGIC; -- afi_reset.reset_n
mem_a : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); -- memory.mem_a
mem_ba : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- .mem_ba
mem_ck : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck
mem_ck_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck_n
mem_cke : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_cke
mem_cs_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_cs_n
mem_dm : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dm
mem_ras_n : OUT STD_LOGIC; -- .mem_ras_n
mem_cas_n : OUT STD_LOGIC; -- .mem_cas_n
mem_we_n : OUT STD_LOGIC; -- .mem_we_n
mem_reset_n : OUT STD_LOGIC; -- .mem_reset_n
mem_dq : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- .mem_dq
mem_dqs : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs
mem_dqs_n : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs_n
mem_odt : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_odt
avl_ready : OUT STD_LOGIC; -- avl.waitrequest_n
avl_burstbegin : IN STD_LOGIC; -- .beginbursttransfer
avl_addr : IN STD_LOGIC_VECTOR(26 DOWNTO 0); -- .address
avl_rdata_valid : OUT STD_LOGIC; -- .readdatavalid
avl_rdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0); -- .readdata
avl_wdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0); -- .writedata
avl_be : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- .byteenable
avl_read_req : IN STD_LOGIC; -- .read
avl_write_req : IN STD_LOGIC; -- .write
avl_size : IN STD_LOGIC_VECTOR(6 DOWNTO 0); -- .burstcount
local_init_done : OUT STD_LOGIC; -- status.local_init_done
local_cal_success : OUT STD_LOGIC; -- .local_cal_success
local_cal_fail : OUT STD_LOGIC; -- .local_cal_fail
seriesterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0); -- oct_sharing.seriesterminationcontrol
parallelterminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0); -- .parallelterminationcontrol
pll_mem_clk : OUT STD_LOGIC; -- pll_sharing.pll_mem_clk
pll_write_clk : OUT STD_LOGIC; -- .pll_write_clk
pll_write_clk_pre_phy_clk : OUT STD_LOGIC; -- .pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : OUT STD_LOGIC; -- .pll_addr_cmd_clk
pll_locked : OUT STD_LOGIC; -- .pll_locked
pll_avl_clk : OUT STD_LOGIC; -- .pll_avl_clk
pll_config_clk : OUT STD_LOGIC; -- .pll_config_clk
dll_delayctrl : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) -- dll_sharing.dll_delayctrl
);
END COMPONENT;
END tech_ddr3_component_pkg;
PACKAGE BODY tech_ddr3_component_pkg IS
END tech_ddr3_component_pkg;
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