Commits · a0e87e618106d762d06ebc53ca352e3dbd892439 · RTSD / HDL · GitLab

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Apr 29, 2015
- Fixed connections to single rank memory · ade1b60b
  Zanting authored 10 years ago
  
  ade1b60b
Apr 22, 2015
- Added DDR3 single rank master and slave · 0b1592e6
  Zanting authored 10 years ago
  
  0b1592e6
Apr 08, 2015
- connected cal_ok and fail · d55d0ad2
  Pepping authored 10 years ago
  
  d55d0ad2
- Removed internal DDR memory model (now needs to be instantiated in tb). Use... · 8e1a6162
  Eric Kooistra authored 10 years ago
  8e1a6162
- Rename ctlr_ref_clk into ref_clk to have simpler and more clear name. · f1cda4e0
  Eric Kooistra authored 10 years ago
  
  f1cda4e0
Mar 11, 2015
- splitted the terminationcontrol lines from the record types... · ed82dce7
  Kenneth Hiemstra authored 10 years ago
  ed82dce7
Jan 08, 2015
- Pass on local_init_done from IP via ctlr_miso.done instead of via separate signal ctlr_init_done. · 37b92e7f
  Eric Kooistra authored 10 years ago
  
  37b92e7f
- Define t_mem_ctlr_mosi/miso in common_mem_pkg, to use that instead of the... · b559785d
  Eric Kooistra authored 10 years ago
  b559785d
Jan 05, 2015
- Rename ctrl into ctlr. · d61c490e
  Eric Kooistra authored 10 years ago
  
  d61c490e
Dec 22, 2014
- Rename ctrl into ctlr. · 8d6b8949
  Eric Kooistra authored 10 years ago
  
  8d6b8949
Dec 19, 2014
- Defined c_ctrl_address_w and c_ctlr_data_w. Corrected soft_reset_n<='1'. Renamed record fields. · 3870acad
  Eric Kooistra authored 10 years ago
  
  3870acad
Dec 18, 2014
- Moved ddr3/ VHDL files to ddr/. · 6d479748
  Eric Kooistra authored 10 years ago
  
  6d479748
- Rename g_ddr into g_tech_ddr · bb69952f
  Eric Kooistra authored 10 years ago
  
  bb69952f
- Gather all DDR parameters in one t_c_tech_ddr record · 3c8fc0e5
  Eric Kooistra authored 10 years ago
  
  3c8fc0e5
Dec 17, 2014
- Added DDR3 IP technology wrapper for straticiv using UniPhy. · 880633c0
  Eric Kooistra authored 10 years ago
  
  880633c0