Captured ICD text for FPGA_beamlet_output_nof_beamlets_RW, for reference in case it needs t obe implemented in future.

HPR-130:

Closes HPR-130

See merge request !365

added rdma packetiser functionality, note that the tb is not done and
will be developed further in HPR-131

Porting ram for Intel Agilex 7

Closes RTSD-181

See merge request !363

Porting ddio/iobuf for Intel Agilex 7

Closes RTSD-209

See merge request !364

Copied from ip_arria10_e2sg_ddio_<ddio_name>_1.vhd and changed technology name to ip_agi027_xxxx. Updated information header.

New IP version for iwave using Agilex 7 (agi027_xxxx) selected variant 10AX115U3F45E2SG. Based on ip_arria10_e2sg/ddio/compile_ip.tcl. Replaced information except description.

Copied from ip_arria10_e2sg/ddio/README.txt. This is file is not updated since ip_arria10. Updated information.

Updated information header. Added library ip_agi027_xxxx_ddio_lib; Added generate-block inclusive the instantiation of a module for the agi027_xxxx.

Updated information. Added component descriptions for ip_agi027_xxxx: ip_agi027_xxxx_ddio_in and ip_agi027_xxxx_ddio_out.

Added the library to hdl_lib_uses_synth for the ip_agi027_xxxx_ddio. Added ip_agi027_xxxx_ddio ip_agi027_xxxx_ddio_lib to hdl_lib_disclose_library_clause_names.

For agilex 7 (agi027_xxxx) is also the ip_agi027_xxxx_ram_rw_rw added, but is is only supporting clock_b. Added library ip_agi027_xxxx_ram_lib.

Copied from ip_arria10_e2sg_ddio_<ddio_name>.vhd and changed technology name to ip_agi027_xxxx. Verified it against generated/altera_gpio_2100/sim/ip_agi027_xxxx_ddio_<ddio_name>_altera_gpio_2100_<hash>.

Create new IPs with the same configuration as the ip_arria10_e2sg_ddio_<ddio_name>.ip. The version for the arria10_e2sg is 19.3.0 and for the agi027_xxxx is 21.0.0.

The README is fully adapted for the Agilex7 and the most important results of the synthesis are reported.

During synthesis, an error occurred. Add remark to information header regarding synthesis error. As a result, the parameter 'read_during_write mode_mixed_ports' is now set to DONT_CARE instead of OLD_DATA.

Based on ip_arria10_e2sg/ram/ip_arria10_e2sg_crw_crw.vhd. Updated information header. Changed the technology_name from ip_arria10_e2sg to ip_agi027_xxxx and crw_crw to rw_rw. And copied in the component declaration from generated/ram_2port_2040/sim/ip_agi027_xxxx_ram_rw_rw_ram_2port_2040_uxwhvmq.vhd and compared it also to ip_arria10_e2sg_crw_crw_ram_2port_2000_zxnv4ey. Checked the differences between this underlying files. The extra generics are added and commented out. The generics that are different address_reg_b, indata_reg_b and outdata_reg_b are changed from “CLOCK1” to “CLOCK0”. Generic read_ng_write_mode_mixed_ports => "OLD_DATA" despite the generated HDL file has default value "DONT_CARE". Changed the ports to one clock. Removed the constant c_outdata_reg_b and change constant c_outdata_reg_a to c_outdata_reg.

Removed duplicate 'ip' in library ip_ip_agi027_xxxx_ram_lib for correct naming as ip_agi027_xxxx_ram_lib.

Removed tb_common_paged_ram_crw_crw from regression_test_vhdl due to its lack of support for simulating buildset iwave and with tb_common_paged_ram_rw_rw taking over.

Create new IP with the similar configuration as the ip_arria10_es2g_ram_crwk_crw.ip and ip_arria10_e2sg_ram_cr_cw.ip, because the use of two read/write ports is not possible by the Agilex. The use of a dual clock is not possible with true dual port, but with one read and one write port it is possible. The version for the arria10_e2sg is 20.0.0 and for the agi027_xxxx is 20.4.0. The ram_name crk_cw is created in stead of crwk_crw.

Removed 'r' character in entity tech_memory_ram_crk_crw for correct naming as tech_memory_ram_crk_cw.

Created due to incompatibility with the standard crwk_crw variant. Based on the ip_arria10_e2sg/ram/ip_arria10_e2sg_crwk_crw.vhd file and copied the component declaration from ip_agi027_xxxx_ram_crk_cw_ram_2port_2040_aadk55y.vhd. Updated information header including a remark with an explanation.

Updated information header e.g: including a remark with an explanation for the modification of the file. Due to that the crwk_crw IP is unavailable for Agilex 7 modified this file to be also compatible with Agilex 7. The modification is based on the architecture of common_ram_crw_crw_ratio.vhd.

Changed the remark from 'See common_paged_ram_crw_crw for details' to 'See common_paged_ram_rw_rw for details', because it uses common_paged_ram_rw_rw and that one is changed. And changed next_page_* to *_next_page.

Created new testbenches based on the architecture of tb_common_paged_ram_crw_crw.vhd, as common_paged_ram_cr_cw and common_paged_ram_rw_rw no longer uses underlying common_paged_ram_crw_crw.

Commented out just added tb_common_paged_ram_ww_rr to regression_test_vhdl due to tb_tb_common_paged_ram_ww_rr was also added.