Merge branch 'HPR-130' into 'master'

HPR-130:

Closes HPR-130

See merge request !365

applications/rdma_demo/libraries/rdma_packetiser/hdllib.cfg

@@ -10,10 +10,8 @@ synth_files =
 
 test_bench_files = 
     tb/vhdl/tb_rdma_packetiser_assemble_header.vhd
-    tb/vhdl/tb_tb_rdma_packetiser_assemble_header.vhd
 
 regression_test_vhdl = 
-    tb/vhdl/tb_tb_rdma_packetiser_assemble_header.vhd
 
 
 [modelsim_project_file]

applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_rdma_packetiser_assemble_header.vhd

@@ -17,7 +17,7 @@
 -- limitations under the License.
 --
 -------------------------------------------------------------------------------
-
+-- NOTE Work in progress, will be finished in HPR-131
 -------------------------------------------------------------------------------
 --
 -- Author: R. vd Walle
@@ -67,12 +67,10 @@ end tb_rdma_packetiser_assemble_header;
 
 architecture tb of tb_rdma_packetiser_assemble_header is
   constant c_dp_clk_period      : time := 5 ns;  -- 200 MHz
+  constant c_mm_clk_period      : time := 1 ns;  -- 1 GHz
   constant c_data_w             : natural := c_word_w;
   constant c_data_init          : natural := 13;
   constant c_hdr_fields_slv_rst : std_logic_vector(1023 downto 0) := (others => '0');
-  constant c_rdma_hdr_len : natural := c_rdma_packetiser_roce_icrc_len + sel_a_b(
-    g_use_immediate,
-    c_rdma_packetiser_roce_hdr_len, c_rdma_packetiser_roce_no_imm_hdr_len);
   constant c_block_len          : natural := g_frame_len * (c_data_w / c_octet_w);
   constant c_dma_len            : natural := c_block_len * g_nof_packets_in_msg;
 
@@ -80,6 +78,8 @@ architecture tb of tb_rdma_packetiser_assemble_header is
 
   signal dp_clk              : std_logic := '1';
   signal dp_rst              : std_logic;
+  signal mm_clk              : std_logic := '1';
+  signal mm_rst              : std_logic;
 
   signal immediate_data      : std_logic_vector(c_word_w - 1 downto 0) := X"89ABCDEF";
   signal block_len           : std_logic_vector(c_halfword_w - 1 downto 0) := TO_UVEC(c_block_len, c_halfword_w);
@@ -89,17 +89,24 @@ architecture tb of tb_rdma_packetiser_assemble_header is
   signal start_address       : std_logic_vector(c_longword_w - 1 downto 0) := std_logic_vector(g_start_address);
 
   signal hdr_fields_slv      : std_logic_vector(1023 downto 0) := (others => '0');
-  signal rx_rdma_header         : t_rdma_packetiser_roce_header;
-  signal exp_rdma_header     : t_rdma_packetiser_roce_header := func_rdma_packetiser_map_header(c_hdr_fields_slv_rst, g_use_immediate);
+  signal rx_rdma_header      : t_rdma_packetiser_roce_header;
+  --signal exp_rdma_header     : t_rdma_packetiser_roce_header := func_rdma_packetiser_map_header(c_hdr_fields_slv_rst, g_use_immediate);
   signal in_en : std_logic := '0';
 
   signal snk_in  : t_dp_sosi := c_dp_sosi_rst;
   signal snk_out : t_dp_siso := c_dp_siso_rdy;
+  signal src_out : t_dp_sosi := c_dp_sosi_rst;
+  signal src_in  : t_dp_siso := c_dp_siso_rdy;
+
+  signal reg_hdr_dat_copi   : t_mem_copi := c_mem_copi_rst;
+  signal reg_hdr_dat_cipo   : t_mem_cipo;
+
 begin
   dp_rst <= '1', '0' after c_dp_clk_period * 7;
   dp_clk <= (not dp_clk) or tb_end after c_dp_clk_period / 2;
-
-  rx_rdma_header <= func_rdma_packetiser_map_header(hdr_fields_slv, g_use_immediate );
+  mm_rst <= '1', '0' after c_mm_clk_period * 7;
+  mm_clk <= (not mm_clk) or tb_end after c_mm_clk_period / 2;
+  --rx_rdma_header <= func_rdma_packetiser_map_header(hdr_fields_slv, g_use_immediate );
 
   p_dp_stimuli : process
   begin
@@ -115,92 +122,25 @@ begin
     wait;
   end process;
 
-  -- check if values in rdma_packetiser_assemble_header match with expected values
-  p_verify_rdma_header : process
-    variable v_exp_ip_total_length      : natural;
-    variable v_exp_udp_total_length     : natural;
-    variable v_exp_bth_opcode           : std_logic_vector(c_byte_w - 1 downto 0);
-    variable v_exp_bth_psn              : natural;
-    variable v_exp_reth_virtual_address : unsigned(c_longword_w - 1 downto 0);
-    variable v_exp_reth_dma_length      : natural;
-    variable v_exp_immediate_data       : std_logic_vector(c_word_w - 1 downto 0);
-    variable v_p, v_m                   : natural := 0;
-  begin
-    for rep in 0 to g_nof_rep - 1 loop
-      proc_common_wait_until_high(dp_clk, snk_in.sop);  -- wait for sop
-
-      v_exp_ip_total_length      := c_network_ip_header_len + c_network_udp_header_len + c_rdma_hdr_len + to_uint(block_len);
-      v_exp_udp_total_length     := c_network_udp_header_len + c_rdma_hdr_len + to_uint(block_len);
-      v_exp_bth_psn              := v_p;
-      v_exp_reth_virtual_address := g_start_address + to_unsigned((v_m mod g_nof_msg) * c_dma_len, c_longword_w);
-      v_exp_reth_dma_length      := c_dma_len;
-      v_exp_immediate_data       := sel_a_b(g_use_immediate,
-      sel_a_b(g_use_msg_cnt_as_immediate, to_uvec((v_m mod g_nof_msg), c_word_w), immediate_data), to_uvec(0, c_word_w));
-
-      -- determine expected opcode
-      if v_p mod g_nof_packets_in_msg = 0 then
-        v_exp_bth_opcode := c_rdma_packetiser_opcode_uc_write_first;
-        if g_nof_packets_in_msg = 1 and g_use_immediate then
-          v_exp_bth_opcode := c_rdma_packetiser_opcode_uc_write_only_imm;
-        elsif g_nof_packets_in_msg = 1 then
-          v_exp_bth_opcode := c_rdma_packetiser_opcode_uc_write_only;
-        end if;
-      elsif v_p mod g_nof_packets_in_msg = g_nof_packets_in_msg - 1 then
-        v_exp_bth_opcode := c_rdma_packetiser_opcode_uc_write_last;
-        if g_use_immediate then
-          v_exp_bth_opcode := c_rdma_packetiser_opcode_uc_write_last_imm;
-        end if;
-      else
-        v_exp_bth_opcode := c_rdma_packetiser_opcode_uc_write_middle;
-      end if;
-
-      -- increase counters
-      v_p := v_p + 1;
-      v_m := v_p / g_nof_packets_in_msg;
-
-      -- assign expected values to signal to view in wave window.
-      exp_rdma_header.ip.total_length      <= to_uvec(v_exp_ip_total_length, c_halfword_w);
-      exp_rdma_header.udp.total_length     <= to_uvec(v_exp_udp_total_length, c_halfword_w );
-      exp_rdma_header.bth.opcode           <= v_exp_bth_opcode;
-      exp_rdma_header.bth.psn              <= to_uvec(v_exp_bth_psn, c_word_w);
-      exp_rdma_header.reth.virtual_address <= std_logic_vector(v_exp_reth_virtual_address);
-      exp_rdma_header.reth.dma_length      <= to_uvec(v_exp_reth_dma_length, c_word_w);
-      exp_rdma_header.immediate_data       <= v_exp_immediate_data;
-      proc_common_wait_some_cycles(dp_clk, 1);
-
-      -- assert when header is not as expected.
-      assert rx_rdma_header                      = exp_rdma_header                      report "Wrong rx_rdma_header" severity error;
-      assert rx_rdma_header.ip.total_length      = exp_rdma_header.ip.total_length      report "Wrong rx_rdma_header.ip.total_length value" severity error;
-      assert rx_rdma_header.udp.total_length     = exp_rdma_header.udp.total_length     report "Wrong rx_rdma_header.udp.total_length value" severity error;
-      assert rx_rdma_header.bth.opcode           = exp_rdma_header.bth.opcode           report "Wrong rx_rdma_header.bth.opcode value" severity error;
-      assert rx_rdma_header.bth.psn              = exp_rdma_header.bth.psn              report "Wrong rx_rdma_header.bth.psn value" severity error;
-      assert rx_rdma_header.reth.virtual_address = exp_rdma_header.reth.virtual_address report "Wrong rx_rdma_header.reth.virtual_address value" severity error;
-      assert rx_rdma_header.reth.dma_length      = exp_rdma_header.reth.dma_length      report "Wrong rx_rdma_header.reth.dma_length value" severity error;
-      assert rx_rdma_header.immediate_data       = exp_rdma_header.immediate_data       report "Wrong rx_rdma_header.immediate_data value" severity error;
-    end loop;
-
-    proc_common_wait_some_cycles(dp_clk, 100);
-    tb_end <= '1';
-    wait;
-  end process;
-
   u_dut: entity work.rdma_packetiser_assemble_header
     generic map (
-      g_use_immediate            => g_use_immediate,
-      g_use_msg_cnt_as_immediate => g_use_msg_cnt_as_immediate
+      g_data_w => 512
     )
     port map (
       st_clk             => dp_clk,
       st_rst             => dp_rst,
+      mm_clk             => mm_clk,
+      mm_rst             => mm_rst,
+
+      reg_hdr_dat_copi   => reg_hdr_dat_copi,
+      reg_hdr_dat_cipo   => reg_hdr_dat_cipo,
 
       snk_in             => snk_in,
-      hdr_fields_slv     => hdr_fields_slv,
+      snk_out            => snk_out,
+      
+      src_out            => src_out,
+      src_in             => src_in,
 
-      immediate_data     => immediate_data,
-      block_len          => block_len,
-      nof_packets_in_msg => nof_packets_in_msg,
-      nof_msg            => nof_msg,
-      dma_len            => dma_len,
-      start_address      => start_address
+      block_len          => block_len
     );
 end tb;

libraries/base/common/src/vhdl/common_field_pkg.vhd

@@ -73,6 +73,8 @@ package common_field_pkg is
   function field_map_out     (field_arr : t_common_field_arr; word_arr   : std_logic_vector; word_w : natural                ) return std_logic_vector;  -- returns slv_out
   function field_map         (field_arr : t_common_field_arr; word_arr_in: std_logic_vector; word_arr_out: std_logic_vector; word_w : natural) return std_logic_vector;  -- returns word_arr
 
+  function field_select_subset(subset_field_arr : t_common_field_arr; larger_field_arr : t_common_field_arr; larger_slv : std_logic_vector) return std_logic_vector;  -- returns subset slv
+
   function field_ovr_arr(field_arr : t_common_field_arr; ovr_init: std_logic_vector) return t_common_field_arr;
 
   function field_exists(field_arr : t_common_field_arr; name: string) return boolean;
@@ -295,6 +297,25 @@ package body common_field_pkg is
     return v_word_arr;
   end field_map;
 
+  function field_select_subset(subset_field_arr : t_common_field_arr; larger_field_arr : t_common_field_arr; larger_slv : std_logic_vector) return std_logic_vector is
+  -- Return SLV mapped to "subset_field_arr" extracted from a larger SLV mapped to "larger_field_arr".
+    variable v_hi_sub  : natural;
+    variable v_lo_sub  : natural;
+    variable v_hi_full : natural;
+    variable v_lo_full : natural;
+    variable out_slv   : std_logic_vector(larger_slv'range) := (others => '0');
+
+  begin
+    for j in subset_field_arr'range loop
+      v_hi_sub  := field_hi(subset_field_arr, j);
+      v_lo_sub  := field_lo(subset_field_arr, j);
+      v_hi_full := field_hi(larger_field_arr, subset_field_arr(j).name);
+      v_lo_full := field_lo(larger_field_arr, subset_field_arr(j).name);
+      out_slv(v_hi_sub downto v_lo_sub) := larger_slv(v_hi_full downto v_lo_full);
+    end loop;
+    return out_slv;
+  end field_select_subset;
+
   function field_ovr_arr(field_arr : t_common_field_arr; ovr_init: std_logic_vector) return t_common_field_arr is
   -- Copy field_arr but change widths to 1 to create a 1-bit override field for each field in field_arr.
     variable v_ovr_field_arr : t_common_field_arr(field_arr'range);

libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd

@@ -58,8 +58,8 @@ entity dp_offload_tx_v3 is
     g_pipeline_ready : boolean := false
   );
   port (
-    mm_rst               : in  std_logic;
-    mm_clk               : in  std_logic;
+    mm_rst               : in  std_logic := '0';
+    mm_clk               : in  std_logic := '0';
 
     dp_rst               : in  std_logic;
     dp_clk               : in  std_logic;