Based on ip_arria10_e2sg/ram/ip_arria10_e2sg_crw_crw.vhd. Updated information...

Based on ip_arria10_e2sg/ram/ip_arria10_e2sg_crw_crw.vhd. Updated information header. Changed the technology_name from ip_arria10_e2sg to ip_agi027_xxxx and crw_crw to rw_rw. And copied in the component declaration from generated/ram_2port_2040/sim/ip_agi027_xxxx_ram_rw_rw_ram_2port_2040_uxwhvmq.vhd and compared it also to ip_arria10_e2sg_crw_crw_ram_2port_2000_zxnv4ey. Checked the differences between this underlying files. The extra generics are added and commented out. The generics that are different address_reg_b, indata_reg_b and outdata_reg_b are changed from “CLOCK1” to “CLOCK0”. Generic read_ng_write_mode_mixed_ports => "OLD_DATA" despite the generated HDL file has default value "DONT_CARE". Changed the ports to one clock. Removed the constant c_outdata_reg_b and change constant c_outdata_reg_a to c_outdata_reg.