Captured ICD text for FPGA_beamlet_output_nof_beamlets_RW, for reference in...

Captured ICD text for FPGA_beamlet_output_nof_beamlets_RW, for reference in case it needs t obe implemented in future.

applications/lofar2/doc/prestudy/FPGA_beamlet_output_nof_beamlets_RW.txt

+Draft text for FPGA_beamlet_output_nof_beamlets_RW, Eric Kooistra, nov 2023
+. Could be used in ICD if we still have to implement this CP.
+. Not supported in current SDPFW (L2TS, Nov 2023).
+
+ICD SC - SDP
+
+4.8.2 FPGA_beamlet_output_nof_beamlets_RW
+
+Using N_beamlets_out = FPGA_beamlet_output_nof_beamlets_RW it is possible to throttle the number of beamlets N_beamlets_out that is output, to less than N_beamlets_ctrl. The purpose is e.g. to reduce N_beamlets_out for low band and increase N_beamlets_out for high band, to make the Station total number of output beamlets still fit on the limited capacity of the 10GbE link from a Station to CEP [Change request AD-13].
+
+Figure 4.1 shows how N_beamlets_out relates to N_beamlets_ctrl (see Figure 3.1 for how N_beamlets_ctrl relates to N_beamlets_sdp). Note that FPGA_beamlet_output_nof_beamlets_RW applies to all beamsets. The SDPTR takes care that the N_beamlets_out setting is applied correctly per beamset, so when N_beamlets_out = N > 488, then beamset 0 will output beamlets 0:487 and beamset 1 will output the remaining beamlets [488:N-1]. If the output of a beamset gets throttled to 0, then the BF packet output for that beamset stops, because then there is no more beamlet data to sent, this can happen when:
+
+ * for beamset 0 when N_beamlets_out = 0 and N_beamsets_ctrl = 1 or 2,
+ * for beamset 1 when N_beamlets_out <= S_sub_bf = 488 and N_beamsets_ctrl = 2,
+ * so in general for beamset i when N_beamlets_out <= i * S_sub_bf and N_beamsets_ctrl > i.
+
+
+geel = Beamlets controlled by SC and output by SDP.
+gray = Beamlets controlled by SC, but not output.
+
+M <= N = N_beamlets_ctrl
+
+|<-- N_beamlets_out = M -->|
+|<-- N_beamlets_ctrl = N ------------------->|
+|    beamlets[0:M-1]       | beamlets[M:N-1] |
+|0     geel            M-1 | M  grey     N-1 |
+
+ * N_beamsets_ctrl = 1, N_beamlets_ctrl = N = 488
+ * N_beamsets_ctrl = 2, N_beamlets_ctrl = N = 976
+
+Figure 4.1 (confluence name: n_beamlets) : Number of beamlets output N_beamlets_out in relation to N_beamsets_ctrl.
+
+
+ICD SDPTR - SDPFW
+
+4.7.1 FPGA_beamlet_output_nof_beamlets_RW
+
+TODO: REG_DP_BLOCK_RESIZE with eop_index field is not yet supported in the SDPFW.
+
+The number  of beamlets denotes dual polarization beamlets, so the block size in number of single polarization beamlet, complex data words is FPGA_beamlet_output_nof_beamlets_RW * N_pol_bf. Therefore the eop_index value contains a factor N_pol_bf = 2.
+
+The procedure to determine the REG_DP_BLOCK_RESIZE setting per beamset from FPGA_beamlet_output_nof_beamlets_RW is (as shown in [AD-4]):
+
+    # Control request FPGA_beamlet_output_nof_beamlets_RW
+    K = S_sub_bf
+    N = FPGA_beamlet_output_nof_beamlets_RW
+    for bset in range(N_beamsets_ctrl):
+        if (bset + 1) * K < N:
+            # still at least K beamlets left, so output full block with K
+            # beamlet indices: [bset * K : (bset + 1) * K - 1]
+            REG_DP_BLOCK_RESIZE[bset].eop_index = N_pol_bf * K - 1
+        elif bset * K < N:
+            # some, but less than K beamlets remaining, so 1 <= R < K
+            R = N - bset * K
+            # output last block with remaining R beamlet indices: [bset * K:(bset + 1) * K - 1]
+            REG_DP_BLOCK_RESIZE[bset].eop_index = N_pol_bf * R - 1
+        else:
+            # no more beamlets remaining, so R = 0
+            REG_DP_BLOCK_RESIZE[bset].eop_index = -1  # eop_index < sop_index (= 0) stop output blocks
+
+
+The procedure to derive the FPGA_beamlet_output_nof_beamlets_RW value from REG_DP_BLOCK_RESIZE settings is:
+
+    # Monitor request FPGA_beamlet_output_nof_beamlets_R
+    N = 0
+    for bset in range(N_beamsets_ctrl):
+        # accumulate of number of beamlets in all beamsets
+        R = (REG_DP_BLOCK_RESIZE[bset].eop_index + 1) / N_pol_bf  # block size R = eop_index - sop_index + 1, sop_index = 0
+        N += R
+    FPGA_beamlet_output_nof_beamlets_R = N