Create new IP with the similar configuration as the ip_arria10_es2g_ram_crwk_crw.ip and ip_arria10_e2sg_ram_cr_cw.ip, because the use of two read/write ports is not possible by the Agilex. The use of a dual clock is not possible with true dual port, but with one read and one write port it is possible. The version for the arria10_e2sg is 20.0.0 and for the agi027_xxxx is 20.4.0. The ram_name crk_cw is created in stead of crwk_crw.
| Name | Last commit | Last update |
|---|---|---|
| applications | ||
| boards | ||
| doc | ||
| libraries | ||
| .gitignore | ||
| .gitlab-ci.yml | ||
| hdl_user_components.ipx | ||
| init_hdl.sh | ||
| readme.md | ||
| tox.ini | ||
| vsg_config.yaml |
HDL linting is using gitlab-runners on dop349.
Linting tool used is vhdl-style-guide (VSG)
link: https://vhdl-style-guide.readthedocs.io/en/latest/index.html
By default all rules are disabled in de vsg_config.yaml file.
The only active rule on this moment is case.keyword and is set to upper.