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Commit d436c4cb authored by David Brouwer's avatar David Brouwer
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Merge branch 'master' into RTSD-181

parents 51819c68 7ad0797b
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1 merge request!363Porting ram for Intel Agilex 7
Checking pipeline status
...@@ -177,12 +177,15 @@ begin ...@@ -177,12 +177,15 @@ begin
v_last.channel := TO_DP_CHANNEL(g_channel_init + (g_nof_repeat - 1) * g_channel_incr); v_last.channel := TO_DP_CHANNEL(g_channel_init + (g_nof_repeat - 1) * g_channel_incr);
v_last.err := TO_DP_ERROR(g_err_init + (g_nof_repeat - 1) * g_err_incr); v_last.err := TO_DP_ERROR(g_err_init + (g_nof_repeat - 1) * g_err_incr);
-- . account for g_pkt_len -- . account for g_pkt_len
v_last.data := INCR_UVEC(v_sosi.data, g_pkt_len - 1); if g_use_complex = false then
v_last.data := RESIZE_DP_DATA(v_last.data(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w v_last.data := INCR_UVEC(v_sosi.data, g_pkt_len - 1);
v_last.re := INCR_UVEC(v_sosi.re, g_pkt_len - 1); v_last.data := RESIZE_DP_DATA(v_last.data(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
v_last.re := RESIZE_DP_DSP_DATA(v_last.re(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w else
v_last.im := INCR_UVEC(v_sosi.im, g_pkt_len - 1); v_last.re := INCR_UVEC(v_sosi.re, g_pkt_len - 1);
v_last.im := RESIZE_DP_DSP_DATA(v_last.im(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w v_last.re := RESIZE_DP_DSP_DATA(v_last.re(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
v_last.im := INCR_UVEC(v_sosi.im, g_pkt_len - 1);
v_last.im := RESIZE_DP_DSP_DATA(v_last.im(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
end if;
last_snk_in <= v_last; last_snk_in <= v_last;
-- Signal end of stimuli -- Signal end of stimuli
......
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