- Added io_ddr to the testbench after removing it from the DUT. 

-Updated port map to interface with external io_ddr

- Added tech generics
- Removed old ddr3 generics
- Updated porttypes
- replaced ddr3 by io_ddr

-Changed all ddr3 references to io_ddr
-Renamed and removed some portnames
-CHanged the ouptut definition of address and burstsize  

The IP is generated with  --allow-mixed-language-simulation option, this affects the paths in the msim_setup.tcl and therefore the compile_ip.tcl

The IP is generated with  --allow-mixed-language-simulation option, this affects the paths in the msim_setup.tcl and therefore the compile_ip.tcl

Added g_sim, when TRUE then use internal DDR memory model in tech_ddr component. When FALSE use DDR memory model in test bench.

Only need to reset the state reg, do not reset the other signals to easy timing closure. Use natural for burst_wr_cnt instead of slv.