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RTSD
HDL
Commits
3f059628731682f15f8b6422f19c7ca57481ae99
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hdl
libraries
io
ddr3
src
vhdl
ddr3.vhd
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Apr 08, 2015
Replaced port types
· 3f059628
Pepping
authored
10 years ago
3f059628
changed phy_ records conform RadioHDL pinning file
· de5ee252
Kenneth Hiemstra
authored
10 years ago
de5ee252
Apr 07, 2015
changed the IP to ip_stratixiv_ddr3_master_800
· ff4e4867
Kenneth Hiemstra
authored
10 years ago
ff4e4867
Apr 02, 2015
Added default values fro MM
· 2eabad81
Pepping
authored
10 years ago
2eabad81
Added default values to mm_Rst and mm_clk
· 800591ef
Pepping
authored
10 years ago
800591ef
Added mm ports
· 7c71ba31
Pepping
authored
10 years ago
7c71ba31
Added mem library
· 5566b292
Pepping
authored
10 years ago
5566b292
Added register map to read out DDR3 uniphy status signals
· 5f54085b
Pepping
authored
10 years ago
5f54085b
update
· ed5fdb06
Kenneth Hiemstra
authored
10 years ago
ed5fdb06
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Kenneth Hiemstra authored
Kenneth Hiemstra authored