Commits · 16ff9a6dd8dcc68e5ba72d36cdb45954590aa633 · RTSD / HDL · GitLab

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Sep 11, 2015
- added gluelogic for the 4x chan 10G IPs · 16ff9a6d
  Kenneth Hiemstra authored 9 years ago
  
  16ff9a6d
- added possible 10G channel configs · c066bd8f
  Kenneth Hiemstra authored 9 years ago
  
  c066bd8f
Sep 09, 2015
- deleted because correct name is ip_arria10_pll_xgmii_mac_clocks.qsys · c63d6b56
  Kenneth Hiemstra authored 9 years ago
  
  c63d6b56
Aug 29, 2015
- moved to ATXPLL driving 12 PHY's instead of 24 · e1e5d150
  Kenneth Hiemstra authored 9 years ago
  
  e1e5d150
- moved to ATXPLL driving 12 PHY's instead of 24 · c80abada
  Kenneth Hiemstra authored 9 years ago
  
  c80abada
Aug 18, 2015
- changed the ATXPLL selecting from 1-24 to 1-12. Either 1 ATXPLL will · aaf62b8f
  Kenneth Hiemstra authored 9 years ago
  
  drive 1xPHY or 1 ATXPLL will drive 12xPHY (recommented by Altera)
  aaf62b8f
- added ddr4_4g_2000 IP · 08d9a16e
  Kenneth Hiemstra authored 9 years ago
  
  08d9a16e
- 10G PHY. 12 channels driven by 1 ATXPLL · 7620fd87
  Kenneth Hiemstra authored 9 years ago
  
  7620fd87
- based on ddr4_4g_1600 but changed clock/timings · dcf1dc3b
  Kenneth Hiemstra authored 9 years ago
  
  dcf1dc3b
Aug 17, 2015
- Reverted edit in path · 45ef5f3e
  Pepping authored 9 years ago
  
  45ef5f3e
Aug 14, 2015
- Fixed qip file folder · 2535e8d7
  Zanting authored 9 years ago
  
  2535e8d7
Aug 13, 2015
- working version for DDR4 using bank mb_I and mb_II (settings are used · 08d50252
  Kenneth Hiemstra authored 9 years ago
  
  from ddr4 testing version ddr4_micron_46)
  08d50252
- changed c_tech_ddr4_max to use a dual rank DDR4 as single rank (see · e39ca9bd
  Kenneth Hiemstra authored 9 years ago
  
  CS1_n, CKE1, ODT1 in tech_ddr_arria10.vhd)
  e39ca9bd
- using a dual rank DDR4 but the IP is single rank: disabling 2nd rank by · 0e2b1046
  Kenneth Hiemstra authored 9 years ago
  
  setting CS1_n=1, CKE1=0 and ODT1=0
  0e2b1046
- Changed PLL and DLL from Slave to Master as was the case with the dual rank ddr3 slave. · debc815c
  Zanting authored 9 years ago
  
  debc815c
Aug 12, 2015
- Added copy hex files script for DDR3 slave UniPHY ip · 1131ff16
  Zanting authored 9 years ago
  
  1131ff16
Jul 16, 2015
- Removed g_link_status_check from tech_eth_10g entity. Added g_direction =... · e5b58438
  Eric Kooistra authored 9 years ago
  
  Removed g_link_status_check from tech_eth_10g entity. Added g_direction = TX_RX default or TX_ONLY, RX_ONLY. Implemented TX_ONLY by internal loopback of MAC Tx xgmii to MAX Rx.
  e5b58438
- Removed g_link_status_check from tech_eth_10g entity. · 24d5f8f2
  Eric Kooistra authored 9 years ago
  
  24d5f8f2
- Improved comment on link_fault. · 797e0a48
  Eric Kooistra authored 9 years ago
  
  797e0a48
Jul 15, 2015
- Explained g_link_status_check and g_pre_header_padding. · 6a100b57
  Eric Kooistra authored 9 years ago
  
  6a100b57
- Added tx_unidir_control via MM in comment. · 71914bb4
  Eric Kooistra authored 9 years ago
  
  71914bb4
- Added eplanation of link fault operation. · 7372d3df
  Eric Kooistra authored 9 years ago
  
  7372d3df
Jun 26, 2015
- Improved legenda of cs_w and cs_w_w in table. · 3f0a25a0
  Eric Kooistra authored 9 years ago
  
  3f0a25a0
Jun 25, 2015
- Added link status MM register reg_eth10g_mosi for ETH10G. · 89d902f0
  Eric Kooistra authored 9 years ago
  
  89d902f0
Jun 24, 2015
- -Removed unused signals and constants. · 588a8417
  Daniel van der Schuur authored 9 years ago
  
  588a8417
- -Changed name of generate and instance name to match entity name to ease wave · d2af806a
  Daniel van der Schuur authored 9 years ago
  
  window navigation in simulation.
  d2af806a
Jun 23, 2015
- Default mts=1600 for DDR4 sim models · bf002039
  Eric Kooistra authored 9 years ago
  
  bf002039
- Use dedicated MB ref_clk input instead of via t_tech_ddr4_phy_in. · 109f99ce
  Eric Kooistra authored 9 years ago
  
  109f99ce
Jun 15, 2015
- added the required ref_clk to the IN record for ddr4 · ea595fc2
  Kenneth Hiemstra authored 9 years ago
  
  ea595fc2
Jun 12, 2015
- Moved DDR sim model to sim_ddr.vhd. · 201f8808
  Eric Kooistra authored 9 years ago
  
  201f8808
- Connected cal_ok and cal_fail.diff · c85011f5
  Eric Kooistra authored 9 years ago
  
  c85011f5
- Added c_tech_ddr3_sim_* and c_tech_ddr4_sim_* constants. Added func_tech_sel_ddr() for boolean. · a0a9e860
  Eric Kooistra authored 9 years ago
  
  a0a9e860
Jun 09, 2015
- original func_tech_ddr_ctlr_data_w() function but needs fix for DDR4 · 61aa2a1f
  Kenneth Hiemstra authored 9 years ago
  
  61aa2a1f
Jun 08, 2015
- Moved ip_arria10_ddr4_mem_model_141 library to hdl_lib_uses_sim section. · da9bf9bc
  Eric Kooistra authored 9 years ago
  
  da9bf9bc
Jun 05, 2015
- [temporary fix] for Quartus compilation. Agree on width in · 27875325
  Kenneth Hiemstra authored 9 years ago
  
  common_fifo_dc_mixed_widths.vhd Line 153
  27875325
May 29, 2015
- added the fractional pll for clk125 · c2d42821
  Kenneth Hiemstra authored 9 years ago
  
  c2d42821
May 28, 2015
- singlemac design and IP compiles with Q15.0 · 32b476fc
  Jonathan Hargreaves authored 9 years ago
  
  32b476fc
May 27, 2015
- added the fractional pll IP for clk125 · 9cac1149
  Kenneth Hiemstra authored 9 years ago
  
  9cac1149
May 22, 2015
- Added global clock buffer IP · a0e87e61
  Eric Kooistra authored 9 years ago
  
  a0e87e61
- Added fractional PLL IP with similar c0, c1 and c2 as the pll_clk200 IO PLL. · 720496f7
  Eric Kooistra authored 9 years ago
  
  720496f7